IXP45X datasheet(19/148 Pages) INTEL

19 / 148 page

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

August 2006

Datasheet

Document Number: 306261-004US

Datasheet—Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

The NPE is a hardware-multi-threaded processor engine that is used to accelerate

functions that are difficult to achieve high performance in a standard RISC processor.

Each NPE is a 133.32-MHz (which is 4 * OSC_IN input pin) processor core that has self-

contained instruction memory and self-contained data memory that operate in parallel.

Each NPE has 4 K words of instruction memory and 4 K words of data memory.

In addition to having separate instruction/data memory and local-code store, the NPE

supports hardware multi-threading with support for multiple contexts. The support of

hardware multi-threading creates an efficient processor engine with minimal processor

stalls due to the ability of the processor to switch contexts in a single clock cycle, based

on a prioritized/preemptive basis. The prioritized/preemptive nature of the context

switching allows time-critical applications to be implemented in a low-latency fashion —

which is required when processing multi-media applications.

The NPE also connects to several hardware-based coprocessors that are used to

implement functions that are difficult for a processor to implement. These functions

include:

Note:

To determine if the SHA-256/384/512 feature is enabled by a particular software

release, see the Intel® IXP400 Software Programmer’s Guide.

These coprocessors are implemented in hardware, enabling the coprocessors and the

NPE processor core to operate in parallel.

With the addition of the new switching coprocessor (SWCP) and the Ethernet

coprocessors enabled with the Intel® IXP400 Software, functions like a four-port,

Layer-2 switch can be easily implemented using all Intel-based silicon. Also, by using

NPEs to implement switching functions, value added features like VLAN or IP switching

can be easily upgraded using existing silicon. Therefore, speeding up the end

customer’s time to market while keeping product costs the same.

The combined forces of the hardware multi-threading, local-code store, independent

instruction memory, independent data memory, and parallel processing — contained on

the NPE — allows the Intel XScale® processor to be utilized for application purposes.

The multi-processing capability of the peripheral interface functions allows unparalleled

performance to be achieved by the application running on the Intel XScale® processor.

3.1.2

Internal Bus

The internal bus architecture of the IXP45X/IXP46X network processors are designed to

allow parallel processing to occur and to isolate bus utilization, based on particular

traffic patterns. The bus is segmented into four major buses:

• HSS Serialization/ De-serialization

• CRC checking/generation

• DES/3DES/AES

• SHA-1/256/384/512

• MD-5

• HDLC bit stuffing/de-stuffing

• Learning/filtering content addressable

memory

• Media Access Controller

functionality

•UTOPIA Level 2 Framing

• North Advanced, High-Performance Bus

(AHB)

• Memory Port Interface

• South AHB

• Advanced Peripheral Bus

(APB)

IXP45X 数据表(PDF) 19 Page - Intel Corporation

IXP45X 数据表(HTML) 19 Page - Intel Corporation

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