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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

Document Number: 306261-004US

The I2C unit supports both fast-mode operation — at 400 Kbps — and standard mode

— at 100 Kbps. Fast mode logic levels, formats, capacitive loading and protocols

function the same in both modes. The I2C unit does not support I2C 10-bit addressing

or CBUS.

3.1.19

Encryption/Decryption/Authentication - AES/DES/SHA/MD-5

The IXP45X/IXP46X network processors implement on-chip hardware acceleration for

underlying security and authentication algorithms.

The encryption/decryption algorithms supported are AES, single pass AES-CCM, DES,

and triple DES. These algorithms are commonly found when implementing IPSEC, VPN,

WEP, WEP2, WPA, and WPA2.

The authentication algorithms supported are MD-5, SHA-1, SHA-256, SHA-384, and

SHA-512. Inclusion of SHA-384 and SHA-512 allows 256-bit key authentication to pair

up with 256-bit AES support.

Note:

To determine if the SHA-256/384/512 feature is enabled by a particular software

release, see the Intel® IXP400 Software Programmer’s Guide.

3.1.20

Cryptography Unit

The Cryptography Unit implements three major functions:

• Exponentiation Unit (EAU)

• Random Number Generator (RNG)

• Secure Hash Algorithm (SHA function for the RNG)

The EAU supports various large number arithmetic operations. These operations include

modular exponentiation, modular reduction, multiply, add and subtract. These

operations are controlled through a set of memory mapped registers. Parameters for

and results of the operations are written in little-endian ordering into a RAM (contained

within the EAU) which the EAU state machine accesses and also uses for temporary

registers. The arithmetic operations supported by the EAU are used by software

executing in the host processor to build larger cryptographic functions such as signing

and verification procedures. Since the EAU executes only one operation at a time, the

host processor must serialize the required operations to the EAU.

The EAU begins operating after the host processor has moved data into the EAU RAM

and loads the EAU’s command register with an appropriate command. After executing

the command, the EAU appropriately sets its status bits and waits idle until it receives

another command from the host processor.

The RNG unit provides a digital, random-number generation capability. It uses a LFSR

(Linear Feedback Shift Register) to generate a sequence of pseudo-random bits. These

sequences are shifted into a FIFO of 32-bit words, which may be read sequentially from

the random number register. A new word is generated every 32 clocks and the RNG will

buffer 16 of these words at a time.

The output of the RNG should be passed through the SHA engine for added

randomness. The host processor (Intel XScale® processor) is responsible for

implementing this SHA-based, random-number generation. The LFSR also allows one

entropy source. The entropy source is fed in from a PN sequence generator which has a

period of 2^42 - 1. The coefficients for the PN sequence is chosen such that it produces

the maximal sequence length. The coefficients are not mentioned for security reasons.

The coefficients for the 128-stage LSFR are similarly not mentioned here for security

reasons.

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