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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

Document Number: 306261-004US

3.1.13

Internal Bus Performance Monitoring Unit (IBPMU)

The IXP45X/IXP46X network processors contain a performance monitoring unit that

may be used to capture predefined events within the system outside of the Intel

XScale® processor. These features aid in measuring and monitoring various system

parameters that contribute to the overall performance of the processor.

The Performance Monitoring (PMON) facility provided comprises:

• Eight Programmable Event Counters (PECx)

• Previous Master/Slave Register

• Event Selection Multiplexor

The programmable event counters are 27 bits wide. Each counter may be programmed

to observe one event from a defined set of events. An event consists of a set of

parameters which define a start condition and a stop condition.

The monitored events are selected by programming the Event Select Registers (ESR).

3.1.14

Interrupt Controller

The IXP45X/IXP46X network processors implement up to 64 interrupt sources to allow

an extension of the Intel XScale® processor’s FIQ and IRQ interrupt sources. These

sources can originate from some external GPIO pins, internal peripheral interfaces, or

internal logic.

The interrupt controller can configure each interrupt source as an FIQ, IRQ, or disabled.

The interrupt sources tied to Interrupt 0 to 7 can be prioritized. The remaining

interrupts are prioritized in ascending order. For example, Interrupt 8 has a higher

priority than 9, 9 has a higher priority than 10, and 30 has a higher priority that 31.

An additional level of priority can be set for interrupts 32 through 64. This priority

setting gives any interrupt between 32 through 64 priority over interrupts 0 through

31.

3.1.15

Timers

The IXP45X/IXP46X network processors contain four internal timers operating at

66.66 MHz (which is 2* OSC_IN input pin) to allow task scheduling and prevent

software lock-ups. The device has four 32-bit counters:

The Timestamp Timer and the two general-purpose timers have the optional ability to

use a pre-scaled clock. A programmable pre-scaler can be used to divide the input

clock by a 16-bit value. The input clock can be either the APB clock (66.66 MHz) or a

20-ns version of the APB clock (50 MHz). By default all timers use the APB clock.

The 16-bit pre-scale value ranges from divide by 2 to 65,536 and results in a new clock

enable available for the timers that ranges from 33.33 MHz down to 1,017.26 Hz.

The Timestamp Timer also contains a 32-bit compare register that allows an interrupt

to be created at times other than time 0.

• Watch-Dog Timer

• Timestamp Timer

• Two general-purpose Timers

IXP45X 数据表(PDF) 28 Page - Intel Corporation

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