IXP45X datasheet(21/148 Pages) INTEL

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

August 2006

Datasheet

Document Number: 306261-004US

Datasheet—Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

3.1.2.3

Memory Port Interface

The Memory Port Interface (MPI) is a 128-bit bus that provides the Intel XScale®

processor a dedicated interface to the DDRI SDRAM. The Memory Port Interface

operates at 133.32 MHz (which is 4 * OSC_IN input pin).

The Memory Port Interface stores memory transactions from the Intel XScale®

processor which have not been processed by the Memory Controller. The Memory Port

Interface supports eight processor read transactions up to 32 bytes each. That total

equals the maximum number of outstanding transaction the Processor Bus Controller

can support. (That includes processor DCU [4 - load requests to unique cache lines],

IFU [2 - prefetch], IMM [1 - tablewalk], DMM [1 - tablewalk].)

The Memory Port Interface also supports eight processor-posted write transactions up

to 16 bytes each.

Arbitration on the Memory Port Interface is not required due to no contention with

other masters. Arbitration will exist in the DDRI memory controller between all of the

main internal busses.

3.1.2.4

APB Bus

The APB Bus is a 66.66-MHz (which is 2* OSC_IN input pin), 32-bit bus that can be

mastered by the AHB/APB bridge only. The targets of the APB bus can be:

The APB interface is also used as an alternate-path interface to the NPEs and is used

for NPE code download and configuration.

No arbitration is required due to a single master implementation.

3.1.3

MII/SMII Interfaces

The IXP45X/IXP46X network processors can be configured to support up to three MII,

up to three SMII industry-standard, or some combination thereof, media-independent

interface (MII) interfaces. These interfaces are integrated into the IXP45X/IXP46X

network processors with separate media-access controllers and in many cases

independent network processing engines. (See Table 3 for allowable combinations.)

The independent NPEs and MACs allow parallel processing of data traffic on the MII

interfaces and off loading of processing required by the Intel XScale® processor. The

IXP45X/IXP46X network processors are compliant with the IEEE 802.3 specification.

In addition to the MII interfaces, the IXP45X/IXP46X network processors include a

single management data interface that is used to configure and control PHY devices

that are connected to the MII interfaces. The IXP45X/IXP46X network processors

provide support for serial media independent interface (SMII).

• USB 1.1 device controller

• UARTs

• The internal bus performance monitoring unit

(IBPMU)

• All NPEs

• GPIO

• Interrupt controller

• IEEE 1588 Hardware Assist

• Timers

•I2C

• Serial Peripheral Port

Interface

IXP45X 数据表(PDF) 21 Page - Intel Corporation

IXP45X 数据表(HTML) 21 Page - Intel Corporation

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