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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

Document Number: 306261-004US

3.1.4

UTOPIA Level 2

The integrated UTOPIA Level 2 interface works with a network-processing engine core

for several of the IXP45X/IXP46X network processors. The pins of the UTOPIA Level 2

interface are multiplexed with one of the MII/SMII interfaces. (See Table 3 for details.)

The UTOPIA Level 2 interface supports a single- or a multiple-physical-interface

configuration with cell-level or octet-level handshaking. The network processing engine

handles segmentation and reassembly of ATM cells, CRC checking/generation, and

transfer of data to/from memory. This allows parallel processing of data traffic on the

UTOPIA Level 2 interface, off-loading these processing tasks from the Intel XScale®

processor.

The IXP45X/IXP46X network processors are compliant with the ATM Forum, UTOPIA

Level 2 Specification, Revision 1.0.

3.1.5

USB 1.1 Device Interface

The integrated USB 1.1 device interface supports full-speed operation and 16 endpoints

and includes an integrated transceiver.

There are:

• Six isochronous endpoints (three input and three output)

• One control endpoints

• Three interrupt endpoints

• Six bulk endpoints (three input and three output)

3.1.6

USB 2.0 Host Interface

USB Host functionality is implemented on the IXP45X/IXP46X network processors. The

function being performed is defined by the USB 2.0 Specification, maintained by

usb.org.

Not all features defined by the 2.0 specification are supported for this implementation.

The following is a partial list of supported features:

• Host function

•Low-speed interface

• Full-speed interface

•EHCI register interface

The following is a partial list of features not supported:

• Device function

• OTG function

• High-speed interface

3.1.7

PCI Controller

The IXP45X/IXP46X network processors’ PCI controller is compatible with the PCI Local

Bus Specification, Rev. 2.2. The PCI interface is 32-bit compatible bus and capable of

operating as either a host or an option (i.e. not the Host). This PCI implementation

supports 3.3 V I/O only.

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