IXP45X datasheet(29/148 Pages) INTEL

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

August 2006

Datasheet

Document Number: 306261-004US

Datasheet—Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

3.1.16

IEEE 1588 Hardware Assistance

In a distributed control system containing multiple clocks, individual clocks tend to drift

apart. Some kind of correction mechanism is necessary to synchronize the individual

clocks to maintain global time, which is accurate to some clock resolution. The

IEEE 1588 standard for a precision clock synchronization protocol for networked

measurement and control systems can be used for this purpose. The IEEE 1588

standard defines several messages that can be used to exchange timing information.

The IXP45X/IXP46X network processors implement the IEEE 1588 hardware-assist

logic on three of the MII interfaces. Using the hardware assist logic along with software

running on the Intel XScale® processor, a full source or sink capable IEEE-1588

compliant network node can be implemented.

Note:

The IXP455 network processor does not support IEEE 1588 hardware-assist.

3.1.17

Synchronous Serial Port Interface

The IXP45X/IXP46X network processors have a dedicated Synchronous Serial Port

(SSP) interface. The SSP interface is a full-duplex synchronous serial interface. It can

connect to a variety of external analog-to-digital (A/D) converters, audio and telecom

CODECs, and many other devices which use serial protocols for transferring data.

It supports National’s Microwire*, Texas Instruments’* synchronous serial protocol

(SSP), and Motorola's* serial peripheral interface (SPI*) protocol.

The SSP operates in master mode (the attached peripheral functions as a slave), and

supports serial bit rates from 7.2 Kbps to 1.8432 Mbps using the on-chip, 3.6864-MHz

clock, and bit rates from 65.10 Kbps to 16.67 Mbps using a maximum off-chip, 33.33

MHz clock. Serial data formats may range from 4 to 16 bits in length. Two on-chip

FIFOs are 16 entries deep x 16 bits wide. Each 32-bit word from the system fills one

entry in a FIFO using the lower half 16-bits of a 32-bit word.

3.1.18

I2C Interface

The I2C Bus Interface Unit allows the IXP45X/IXP46X network processors to serve as a

master and slave device residing on the I2C bus. The I2C bus is a two-pin serial bus.

SDA is the data pin for input and output functions and SCL is the clock pin for reference

and control of the I2C bus.

The I2C bus allows the IXP45X/IXP46X network processors to interface to other I2C

peripherals and micro-controllers for system management functions. The serial bus

requires a minimum of hardware for an economical system to relay status and

reliability information on the IXP45X/IXP46X network processors subsystem to an

external device.

The I2C Bus Interface Unit is a peripheral device that resides on the IXP45X/IXP46X

network processors’ APB. Data is transmitted to and received from the I2C bus via a

buffered interface. Control and status information is relayed through a set of memory-

mapped registers. Refer to the I2C Bus Specification for complete details on I2C bus

operation.

The I2C supports:

• Multi-master capabilities

• Slave capabilities

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