IXP45X datasheet(45/148 Pages) INTEL

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August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

Table 10.

DDR SDRAM Interface (Sheet 1 of 2)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

DDRI_CK[2:0]

DDR SDRAM Clock Out — Provide the positive differential clocks to the external SDRAM

memory subsystem.

DDRI_CK_N[2:0]

DDR SDRAM Clock Out — Provide the negative differential clocks to the external SDRAM

memory subsystem.

DDRI_CS_N[1:0]

Chip Select — Must be asserted for all transactions to the DDR SDRAM device. One per bank.

DDRI_RAS_N

Row Address Strobe — Indicates that the current address on DDRI_MA[13:0] is the row.

DDRI_CAS_N

Column Address Strobe — Indicates that the current address on DDRI_MA[13:0] is the

column.

DDRI_WE_N

Write Strobe — Defines whether or not the current operation by the DDR SDRAM is to be a

read or a write.

DDRI_DM[4:0]

Data Bus Mask — Controls the DDR SDRAM data input buffers. Asserting DDRI_WE_N causes

the data on DDRI_DQ[31:0] and DDRI_CB[7:0] to be written into the DDR SDRAM devices.

DDRI_DM[4:0] controls this operation on a per byte basis. DDRI_DM[3:0] are intended to

correspond to each byte of a word of data. DDRI_DM[4] is intended to be utilized for the ECC

byte of data.

DDRI_BA[1:0]

DDR SDRAM Bank Selects — Controls which of the internal DDR SDRAM banks to read or write.

DDRI_BA[1:0] are used for all technology types supported.

DDRI_MA[13:0]

Address bits 13 through 0 — Indicates the row or column to access depending on the state of

DDRI_RAS_N and DDRI_CAS_N.

DDRI_DQ[31:0]

I/O

Data Bus — 32-bit wide data bus.

DDRI_CB[7:0]

I/O

ECC Bus — Eight-bit error correction code which accompanies the data on DDRI_DQ[31:0].

When ECC is disabled and not being used in a system design, these signals are not required for

any connection.

DDRI_DQS[4:0]

I/O

Data Strobes Differential — Strobes that accompany the data to be read or written from the

DDR SDRAM devices. Data is sampled on the negative and positive edges of these strobes.

DDRI_DQS[3:0] are intended to correspond to each byte of a word of data. DDRI_DQS4] is

intended to be utilized for the ECC byte of data.

DDRI_CKE[1:0]

b’00

Clock enables — One clock after DDRI_CKE[1:0] is de-asserted, data is latched on DQ[31:0]

and DDRI_CB[7:0]. Burst counters within DDR SDRAM device are not incremented. De-

asserting this signal places the DDR SDRAM in self-refresh mode. For normal operation,

DDRI_CKE[1:0] must be asserted.

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

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