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IXP45X 数据表(PDF) 46 Page - Intel Corporation |
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IXP45X 数据表(HTML) 46 Page - Intel Corporation |
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46 / 148 page ![]() Package Information August 2006 Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet 46 Document Number: 306261-004US DDRI_RCVENOUT_N Z 1 VO VO O RECEIVE ENABLE OUT must be connected to DDRI_RCVENIN_N signal of the IXP45X/IXP46X network processors and the propagation delay of the trace length must be matched to the clock trace plus the average DQ Traces. DDRI_RCVENIN_N Z VI VI VI I RECEIVE ENABLE IN provides delay information for enabling the input receivers and must be connected to the DDRI_RCVENOUT_N signal of the IXP45X/IXP46X network processors. DDRI_RCOMP Tied off to a resistor Tied off to a resistor Tied off to a resistor Tied off to a resistor O 20 Ohm 1% tolerance Resistor connected to ground used for process/temperature adjustments. DDRI_VREF VCCM/2 VCCM/2 VCCM/2 VCCM/2 I DDR SDRAM Voltage Reference — is used to supply the reference voltage to the differential inputs of the memory controller pins. Table 11. PCI Controller (Sheet 1 of 4) Name Power on Reset† Reset† Normal After Reset Until Software Enables Possible Configur ations After Software Enables Type† Description PCI_AD[31:0] Z Z VB VB I/O PCI Address/Data bus used to transfer address and bidirectional data to and from multiple PCI devices. When this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse (refer to Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual) and is not being used in a system design, this interface/ signal is not required for any connection. PCI_CBE_N[3:0] Z Z VB VB I/O PCI Command/Byte Enables is used as a command word during PCI address cycles and as byte enables for data cycles. When this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse (refer to Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual) and is not being used in a system design, this interface/ signal is not required for any connection. Note: This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor, see Table 1 on page 13. † For a legend of the Type codes, see Table 8 on page 43. Table 10. DDR SDRAM Interface (Sheet 2 of 2) Name Power on Reset† Reset† Normal After Reset Until Software Enables Possible Configur ations After Software Enables Type† Description Note: This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor, see Table 1 on page 13. † For a legend of the Type codes, see Table 8 on page 43. |
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