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M41T82 数据表(PDF) 21 Page - STMicroelectronics |
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M41T82 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 61 page  M41T82-M41T83 Clock operation Doc ID 12578 Rev 12 21/61 Table 2. M41T82 clock/control register map (32 bytes)(1) 1. See Table 3: Key to Table 2: M41T82 clock/control register map (32 bytes) Addr Function/range BCD format D7 D6 D5 D4 D3 D2 D1 D0 00h 0.1 seconds 0.01 seconds seconds 00-99 01h ST 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h CB1 CB0 10 hours Hours (24 hour format) Century/hours 0-3/00-23 04h 0 0 0 0 0 Day of week Day 01-7 05h 0 0 10 date Date: day of month Date 01-31 06h 0 0 0 10M Month Month 01-12 07h 10 years Year Year 00-99 08h 0 FT DCS DC4 DC3 DC2 DC1 DC0 Digital calibration 09h 0 BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog 0Ah 0 0 ABE Al1 10M Alarm1 month Al1 month 01-12 0Bh RPT14 RPT15 AI1 10 date Alarm1 date Al1 date 01-31 0Ch RPT13 HT AI1 10 hour Alarm1 hour Al1 hour 00-23 0Dh RPT12 Alarm1 10 minutes Alarm1 minutes Al1 min 00-59 0Eh RPT11 Alarm1 10 seconds Alarm1 seconds Al1 sec 00-59 0Fh WDF AF1 AF2(2) 2. AF2 will always read 0, if the AL2E bit is set to 0. BL TF OF 0 0 Flags 10h Timer countdown value Timer value 11h TE 0 0 0 0 0 TD1 TD0 Timer control 12h ACS AC6 AC5 AC4 AC3 AC2 AC1 AC0 Analog calibration 13h 0 0 0 0 0 0 AL2E 0 SQW 14h 0(3) 3. As indicated in Table 3, the 0 bits should be written to 0. But in the case of these four bits, when AL2E is 0, registers 14-18h are SRAM locations and these bits become SRAM cells which are thus excluded from that restriction. 0(3) 0(3) Al2 10M Alarm2 month SRAM/Al2 month 01-12 15h RPT24 RPT25 AI2 10 date Alarm2 month SRAM/Al2 date 01-31 16h RPT23 0(3) AI2 10 hour Alarm2 date SRAM/Al2 hour 00-23 17h RPT22 Alarm2 10 minutes Alarm2 minutes SRAM/Al2 min 00-59 18h RPT21 Alarm2 10 seconds Alarm2 seconds SRAM/Al2 sec 00-59 19h-1Fh User SRAM (7 bytes) SRAM |
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