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M41T82 数据表(PDF) 42 Page - STMicroelectronics |
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M41T82 数据表(HTML) 42 Page - STMicroelectronics |
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42 / 61 page ![]() Clock operation M41T82-M41T83 42/61 Doc ID 12578 Rev 12 The timer, oscillator fail detect circuit, alarm 1, and watchdog are ORed together as the primary interrupt sources. The frequency test signal, FT, is used to enable a 512 Hz output on the IRQ1/FT/OUT pin for calibrating the RTC. When not used as an interrupt or frequency test output, the pin can be used as a discrete logic output controlled by the OUT bit. The ABE bit is used to enable interrupts during backup mode. Operating on VCC, all four interrupt sources are available. During backup, the timer and watchdog are disabled, and the only interrupt sources are alarm 1 and the oscillator fail detect circuit. 3.14.1 Active mode operation on VCC On VCC, the operation of the output circuit is as shown in Table 15. When OUT is 0 and FT is 0, the pin will be 0 regardless of whether any interrupts are enabled. When FT is a 1, the 512 Hz signal will be output if OUT is 0 or if no interrupts are enabled. The interrupt sources control the pin when OUT is 1 and one or more of the interrupts are enabled. If OUT is 1, FT is 0 and no interrupts are enabled, then the pin will be 1. Table 15. Priority for IRQ1/FT/OUT pin when operating on VCC OUT(1) FT(2) A1IE(3) + OFIE(4) + TIE(5) + watchdog(6) running Pin Comment 00 x 0 When OUT is 0 and FT is not enabled, OUT dominates and none of the interrupt sources have any effect. 01 x 512 Hz When FT = 1 and OUT = 1 and no interrupts are enabled, the output will be the 512 Hz frequency test (FT) signal. x1 0 1x 1 IRQ When one or more interrupts are enabled, and OUT is a 1, the pin stays high until one of the interrupts is asserted. 10 0 1 When OUT is 1, FT is 0 and no interrupts are enabled, the pin is high. 1. OUT is bit 7 of register 08h (digital calibration). 2. FT is bit 6 of register 08h (digital calibration). 3. A1IE is bit 7 of register 0Ah (alarm 1, month). 4. OFIE is bit 7 of register 09h (watchdog). 5. TIE is bit 5 of register 11h (timer control). 6. The watchdog is controlled by register 09h (watchdog). |
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