M41T82 datasheet(34/61 Pages) STMICROELECTRONICS

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Clock operation

M41T82-M41T83

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Doc ID 12578 Rev 12

3.6

Optional second programmable alarm and user SRAM

When the alarm 2 enable (AL2E) bit (D1 of address 13h) is set to a logic 1, registers 14h

through 18h provide control for a second programmable alarm which operates in the same

manner as the alarm function described in Section 3.5. The AL2E bit defaults on initial

power-up to a logic 0 (alarm 2 disabled). In this mode, the five alarm 2 bytes (14h-18h)

function as additional user SRAM, for a total of 12 bytes of user SRAM.

With AL2E set to 1, the alarm is enabled, and will cause the AF2 bit to be set when the

alarm condition is met. On the M41T83, if the A2IE (alarm 2 interrupt enable) bit is set, an

interrupt will be asserted on IRQ2. The interrupt is de-asserted when the alarm flags are

cleared by reading the flags register (0Fh).

IRQ2 can be enabled in backup mode by setting ABE to 1 (in conjuction with setting A2IE).

3.7

Watchdog timer

The watchdog timer can be used to detect an out-of-control microprocessor. The user

programs the watchdog timer by setting the desired amount of time-out into the watchdog

RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second,

and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of

the five-bit multiplier value with the resolution. (For example: writing 00001110 in the

watchdog register = 3*1, or 3 seconds). If the processor does not reset the timer within the

specified period, the M41T8x sets the WDF (watchdog flag).

The watchdog timer is reset by writing to the watchdog register. The time-out period then

starts over.

M41T83 watchdog interrupt

On the M41T83, provided that the necessary configuration bits are set, the IRQ/FT/OUT

output will be asserted when the watchdog times out (see Section 3.14 for additional

conditions which apply).

Should the watchdog time out, to de-assert the IRQ1/FT/OUT output, the lower seven bits of

the watchdog register (09h) must be written. This will de-assert the output and re-initialize

the watchdog. Writing these seven bits to 0 will de-assert the output and disable the

watchdog.

Table 8.

Alarm repeat modes

RPT5

RPT4

RPT3

RPT2

RPT1

Alarm setting

11111

Once per second

11110

Once per minute

11100

Once per hour

11000

Once per day

10000

Once per month

00000

Once per year

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