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STM8L101F2P3ATR 数据表(PDF) 77 Page - STMicroelectronics |
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STM8L101F2P3ATR 数据表(HTML) 77 Page - STMicroelectronics |
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77 / 81 page ![]() STM8L101xx Revision history Doc ID 15275 Rev 11 77/81 12-Jun-2009 6 Removed TSSOP28 package Modified consumption value on first page Added BEEP_CSR (address 00 50F3h) in Table 7: General hardware register map on page 25 TIM2_PSCRL replaced with TIM2_PSCR and CLK_PCKEN replaced with CLK_PCKENR in Table 7: General hardware register map on page 25 Added graphs in Section 9: Electrical parameters on page 37 Added tWU(AH) and tWU(Halt) max values in Table 20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V on page 44 Modified Table 20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V on page 44 Updated Table 22: HSI oscillator characteristics on page 46, Table 23: LSI oscillator characteristics on page 47 and Table 24: RAM and hardware registers on page 49 Modified Table 27: Output driving current (standard ports) on page 53 Removed note 1 in Table 37: Electrical sensitivities on page 64 Added note to Table 39: UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5), package mechanical data on page 67 and Table 41: UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4), package mechanical data on page 70 Table 44. Document revision history (continued) Date Revision Changes |
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