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MPC5601DXLL 数据表(PDF) 38 Page - Freescale Semiconductor, Inc |
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MPC5601DXLL 数据表(HTML) 38 Page - Freescale Semiconductor, Inc |
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38 / 77 page ![]() MPC5602D Microcontroller Data Sheet, Rev. 3.1 Preliminary—Subject to Change Without Notice Electrical characteristics Freescale Semiconductor 38 4.9.2 Voltage monitor electrical characteristics The device implements a power-on reset (POR) module to ensure correct power-up initialization, as well as four low voltage detectors (LVDs) to monitor the VDD and the VDD_LV voltage while device is supplied: • POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state • LVDHV3 monitors VDD to ensure device reset below minimum functional supply • LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range • LVDLVCOR monitors power domain No. 1 • LVDLVBKP monitors power domain No. 0 NOTE When enabled, power domain No. 2 is monitored through LVD_DIGBKP. Figure 8. Low voltage monitor vs. reset 3 This capacitance value is driven by the constraints of the external voltage regulator supplying the V DD_BV voltage. A typical value is in the range of 470 nF. 4 This value is acceptable to guarantee operation from 4.5 V to 5.5 V. 5 External regulator and capacitance circuitry must be capable of providing I DD_BV while maintaining supply VDD_BV in operating range. 6 In-rush current is seen only for short time during power-up and on standby exit (max 20 µs, depending on external capacitances to be load). VDD VLVDHVxH RESET VLVDHVxL |
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