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MPC5601DXLL 数据表(PDF) 62 Page - Freescale Semiconductor, Inc |
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MPC5601DXLL 数据表(HTML) 62 Page - Freescale Semiconductor, Inc |
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62 / 77 page  MPC5602D Microcontroller Data Sheet, Rev. 3.1 Preliminary—Subject to Change Without Notice Electrical characteristics Freescale Semiconductor 62 4.18.2 DSPI characteristics Table 40. DSPI characteristics1 1 Operating conditions: C OUT = 10 to 50 pF, Slew IN = 3.5 to 15 ns. No. Symbol C Parameter DSPI0/DSPI1 Unit Min Typ Max 1tSCK SR D SCK cycle time Master mode (MTFE = 0) 125 — — ns D Slave mode (MTFE = 0) 125 — — D Master mode (MTFE = 1) 83 — — D Slave mode (MTFE = 1) 83 — — —fDSPI SR D DSPI digital controller frequency — — fCPU MHz — t CSC CC D Internal delay between pad associated to SCK and pad associated to CSn in master mode Master mode — — 1302 2 Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad. ns — t ASC CC D Internal delay between pad associated to SCK and pad associated to CSn in master mode for CSn1 1 Master mode — — 130(2) ns 2tCSCext 3 3 The t CSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than t CSC to ensure positive tCSCext. SR D CS to SCK delay Slave mode 32 — — ns 3tASCext 4 SR D After SCK delay Slave mode 1/fDSPI + 5 — — ns 4tSDC CC D SCK duty cycle Master mode — tSCK/2 — ns SR D Slave mode tSCK/2 — — 5tA SR D Slave access time — 1/fDSPI +70 — — ns 6tDI SR D Slave SOUT disable time — 7 — — ns 9tSUI SR D Data setup time for inputs Master mode 43 — — ns Slave mode 5 — — 10 tHI SR D Data hold time for inputs Master mode 0 — — ns Slave mode 25 —— 11 tSUO 6 CC D Data valid after SCK edge Master mode — — 32 ns Slave mode — — 52 12 tHO (6) CC D Data hold time for outputs Master mode 0 — — ns Slave mode 8 — — |
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