HT68FU50 datasheet(144/244 Pages) HOLTEK

144 / 244 page

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.50

144

March 15, 2011

2C Interface

The I

2C interface is used to communicate with external

peripheral devices such as sensors, EEPROM memory

etc. Originally developed by Philips, it is a two line low

speed serial interface for synchronous serial data trans-

fer. The advantage of only two lines for communication,

relatively simple communication protocol and the ability

to accommodate multiple devices on the same bus has

made it an extremely popular interface type for many

applications.

· I2C Interface Operation

The I

2C serial interface is a two line interface, a serial

data line, SDA, and serial clock line, SCL. As many

devices may be connected together on the same bus,

their outputs are both open drain types. For this rea-

son it is necessary that external pull-high resistors are

connected to these outputs. Note that no chip select

line exists, as each device on the I

2C bus is identified

by a unique address which will be transmitted and re-

ceived on the I

2C bus.

When two devices communicate with each other on

the bidirectional I

2C bus, one is known as the master

device and one as the slave device. Both master and

slave can transmit and receive data, however, it is the

master device that has overall control of the bus. For

these devices, which only operates in slave mode,

there are two methods of transferring data on the I

bus, the slave transmit mode and the slave receive

mode.

There are several configuration options associated

with the I

2C interface. One of these is to enable the

function which selects the SIM pins rather than normal

I/O pins. Note that if the configuration option does not

select the SIM function then the SIMEN bit in the

SIMC0 register will have no effect. A configuration op-

tion determines the debounce time of the I

2C inter-

face. This uses the system clock to in effect add a

debounce time to the external clock to reduce the pos-

sibility of glitches on the clock line causing erroneous

operation. The debounce time, if selected, can be

chosen to be either 2 or 4 system clocks. To achieve

the required I

2C data transfer speed, there exists a re-

lationship between the system clock, fSYS, and the I

debounce time. For either the I

2C Standard or Fast

mode operation, users must take care of the selected

system clock frequency and the configured debounce

time to match the criterion shown in the following ta-

ble.

2C Debounce

Time Selection

2C Standard

Mode (100kHz)

2C Fast Mode

(400kHz)

No debounce

fSYS > 2MHz

fSYS > 5MHz

2 system clock

debounce

fSYS > 4MHz

fSYS > 10MHz

4 system clock

debounce

fSYS > 8MHz

fSYS > 20MHz

2C Minimum f

SYS Frequency

· I

2C Registers

There are three control registers associated with the

2C bus, SIMC0, SIMC1 and SIMA and one data regis-

ter, SIMD. The SIMD register, which is shown in the

above SPI section, is used to store the data being

transmitted and received on the I

2C bus. Before the

microcontroller writes data to the I

2C bus, the actual

data to be transmitted must be placed in the SIMD

2C bus,

the microcontroller can read it from the SIMD register.

Any transmission or reception of data from the I

2C bus

must be made via the SIMD register.

Note that the SIMA register also has the name SIMC2

which is used by the SPI function. Bit SIMEN and bits

SIM2~SIM0 in register SIMC0 are used by the I

2Cin-

terface.

S T A R T s i g n a l

f r o m M a s t e r

S e n d s l a v e a d d r e s s

a n d R / W b i t f r o m M a s t e r

A c k n o w l e d g e

f r o m s l a v e

S e n d d a t a b y t e

f r o m M a s t e r

A c k n o w l e d g e

f r o m s l a v e

S T O P s i g n a l

f r o m M a s t e r

D e v i c e

S l a v e

D e v i c e

M a s t e r

D e v i c e

S l a v e

V D D

S D A

S C L

2C Master Slave Bus Connection

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