Register description

LSM303DLM

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Doc ID 018725 Rev 1

9.1.4

CTRL_REG4_A (23h)

The BDU bit is used to inhibit output register updates between the reading of the upper and

lower register parts. In default mode (BDU = ‘0’), the lower and upper register parts are

updated continuously. If it is not certain whether to read faster than the output data rate, it is

recommended to set BDU bit to ‘1’. In this way, after the reading of the lower (upper) register

part, the content of that output register is not updated until the upper (lower) part is read

also. This feature avoids reading LSB and MSB related to different samples.

LIR2

Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by

reading INT2_SRC itself. Default value: 0.

(0: interrupt request not latched; 1: interrupt request latched)

I2_CFG1,

I2_CFG0

Data signal on INT 2 pad control bits. Default value: 00.

(see

Table 26)

LIR1

Latch interrupt request on INT1_SRC register, with INT1_SRC register cleared by

reading INT1_SRC register. Default value: 0.

(0: interrupt request not latched; 1: interrupt request latched)

I1_CFG1,

I1_CFG0

Data signal on INT 1 pad control bits. Default value: 00.

(see

Table 26)

Table 26.

Data signal on INT 1 and INT 2 pad

I1(2)_CFG1

I1(2)_CFG0

INT 1(2) Pad

0

0

Interrupt 1 (2) source

0

1

Interrupt 1 source OR Interrupt 2 source

1

0

Data ready

1

1

Boot running

Table 25.

CTRL_REG3_A description (continued)

Table 27.

CTRL_REG4_A register

BDU

BLE

FS1

FS0

0

0

1.

This bit must be set to ‘0’ for correct working of the device.

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Table 28.

CTRL_REG4_A description

BDU

Block data update. Default value: 0

(0: continuos update; 1: output registers not updated between MSB and LSB reading)

BLE

Big/little endian data selection. Default value 0.

(0: data LSB @ lower address; 1: data MSB @ lower address)

FS1, FS0

Full-scale selection. Default value: 00.

(00: ±2

g; 01: ±4 g; 11: ±8 g)