LSM303DLM datasheet(32/38 Pages) STMICROELECTRONICS

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LSM303DLM

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Doc ID 018725 Rev 1

9.1.17

INT2_SRC_A (35h)

Interrupt 2 source register. Read-only register.

Reading at this address clears the INT2_SRC_A IA bit (and the interrupt signal on the INT 2

pin) and allows the refreshing of data in the INT2_SRC_A register if the latched option was

chosen.

9.1.18

INT2_THS_A (36h)

9.1.19

INT2_DURATION_A (37h)

Table 48.

INT2_SRC_A register

YHYLXHXL

Table 49.

INT2_SRC_A description

Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Z high. Default value: 0

(0: no interrupt, 1: Z high event has occurred)

Z low. Default value: 0

(0: no interrupt; 1: Z low event has occurred)

Y high. Default value: 0

(0: no interrupt, 1: Y high event has occurred)

Y low. Default value: 0

(0: no interrupt, 1: Y low event has occurred)

X high. Default value: 0

(0: no interrupt, 1: X high event has occurred)

X Low. Default value: 0

(0: no interrupt, 1: X low event has occurred)

Table 50.

INT2_THS register

THS6

THS5

THS4

THS3

THS2

THS1

THS0

Table 51.

INT2_THS description

THS6 - THS0

Interrupt 1 threshold. Default value: 000 0000

Table 52.

INT2_DURATION_A register

D6D5D4

D2D1

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