LSM303DLM datasheet(30/38 Pages) STMICROELECTRONICS

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LSM303DLM

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Doc ID 018725 Rev 1

Interrupt 1 source register. Read-only register.

Reading at this address clears the INT1_SRC_A IA bit (and the interrupt signal on the INT 1

pin) and allows the refreshing of data in the INT1_SRC_A register if the latched option was

chosen.

9.1.14

INT1_THS_A (32h)

9.1.15

INT1_DURATION_A (33h)

The D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized.

Duration steps and maximum values depend on the ODR chosen.

Table 40.

INT1_SRC_A description

Interrupt active. Default value: 0

(0: no interrupt has been generated, 1: one or more interrupts have been generated)

Z high. Default value: 0

(0: no interrupt, 1: Z high event has occurred)

Z low. Default value: 0

(0: no interrupt, 1: Z low event has occurred)

Y high. Default value: 0

(0: no interrupt, 1: Y high event has occurred)

Y low. Default value: 0

(0: no interrupt, 1: Y low event has occurred)

X high. Default value: 0

(0: no interrupt, 1: X high event has occurred)

X low. Default value: 0

(0: no interrupt, 1: X low event has occurred)

Table 41.

INT1_THS register

THS6

THS5

THS4

THS3

THS2

THS1

THS0

Table 42.

INT1_THS description

THS6 - THS0

Interrupt 1 threshold. Default value: 000 0000

Table 43.

INT1_DURATION_A register

D6D5D4

D2D1

Table 44.

INT2_DURATION_A description

D6 - D0

Duration value. Default value: 000 0000

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