LSM303DLM

Register description

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9.1.5

CTRL_REG5_A (24h)

TurnOn bits are used for turning on the sleep-to-wakeup function.

By setting the TurnOn [1:0] bits to 11, the “sleep-to-wakeup” function is enabled. When an

interrupt event occurs, the device goes into normal mode, increasing the ODR to the value

defined in CTRL_REG1_A. Although the device is in normal mode, CTRL_REG1_A content

is not automatically changed to “normal mode” configuration.

9.1.6

HP_FILTER_RESET_A (25h)

Dummy register. Reading at this address instantaneously zeroes the content of the internal

high-pass filter. If the high-pass filter is enabled, all three axes are instantaneously set to 0

g. This makes it possible to surmount the settling time of the high-pass filter.

9.1.7

REFERENCE_A (26h)

This register sets the acceleration value taken as a reference for the high-pass filter output.

When the filter is turned on (at least one FDS, HPen2, or HPen1 bit is equal to ‘1’) and HPM

bits are set to “01”, filter out is generated taking this value as a reference.

Table 29.

CTRL_REG5_A register

0

000

00

TurnOn1

TurnOn0

Table 30.

CTRL_REG5_A description

TurnOn1,

TurnOn0

Turn-on mode selection for sleep-to-wakeup function. Default value: 00.

Table 31.

Sleep-to-wakeup configuration

TurnOn1

TurnOn0

Sleep-to-wakeup status

0

0

Sleep-to-wakeup function is disabled

11

Turned on: the device is in low-power mode

(ODR is defined in CTRL_REG1_A)

Table 32.

REFERENCE_A register

Ref7

Ref6

Ref5

Ref4

Ref3

Ref2

Ref1

Ref0

Table 33.

REFERENCE_A description

Ref7 - Ref0

Reference value for high-pass filter. Default value: 00h.