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SPEAR300 数据表(PDF) 58 Page - STMicroelectronics |
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SPEAR300 数据表(HTML) 58 Page - STMicroelectronics |
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58 / 83 page ![]() Timing requirements SPEAr300 58/83 Doc ID 16324 Rev 2 6.1.2 DDR2 write cycle timings Figure 9. DDR2 Write cycle waveforms Figure 10. DDR2 Write cycle path 166 MHz 2.00 ns 260 ps 133 MHz 2.37 ns 634 ps Table 26. DDR2 Read cycle timings (continued) Frequency t4 max t5 max Table 27. DDR2 Write cycle timings Frequency t4 max t5 max Unit 333 MHz 1.36 -1.55 ns 266 MHz 1.55 -1.36 ns 200 MHz 1.86 -1.05 ns 166 MHz 2.11 - 794 ns 133 MHz 2.49 -420 ns t6 t6 t6 t4 t5 t4 t5 t4 t5 CLK DQS DQ |
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