SPEAR300 datasheet(20/83 Pages) STMICROELECTRONICS

20 / 83 page

Architecture overview

SPEAr300

20/83

Doc ID 16324 Rev 2

2.16

SPI_I2C multiple slave control

The SPI interface has only one slave select signal, SS0.

The I2C interface does not allow control of several devices with the same address, which is

frequently required for CODECs.

The SPI_I2C extension allows management of up to 8 SPI devices, or 8 I2C devices at the

same address (total SPI+I2C devices=8).

The SPI extension is made by generating three more slave select signals SS1, SS2 and

SS3.

The I2C extension is done by replicating the I2C_SCL signal if the corresponding pin is set

active.Otherwise the pin remains low, so that the start condition is not met.

Each of the 8 pins can reproduce either the SPI SS0 signal, or the I2C_SCL signal. The

selection is made through a register.

2.17

TDM interface

The TDM block implements time division multiplexing.

Main features:

●

TDM interface with 512 timeslots and up to 16 bufferization channels.

●

32 ms bufferization for 16 channels (of 4 bytes each)

●

Supports master and slave mode operation

●

Programmable clock and synchronization signal generation in master mode

●

Clock & synchronization signal recovery in slave mode

●

8 programmable synchronization signals for CODECs

●

Uses 11 pins:

–

SYNC7-0 are dedicated frame syncs for CODECs without timeslot recognition

–

CLK is the TDM clock

–

DIN is the TDM input and receives the data

–

DOUT is the TDM output and transmits the data. It can be high impedance on a

unused timeslot

●

The TDM interface can be the master or a slave of the CLK or SYNC0 signals.

●

Timeslots can be used for switching or bufferization purposes:

–

Switching and bufferization can be used concurrently for different timeslots on the

same TDM

–

The only limitation is that an output timeslot can not be switched and bufferized at

the same time.

–

Timeslot switching: any of the output time slots can receive any input timeslot of

the previous frame. The connection memory is part of the action memory,

indicating which timeslot has to be output.

–

Timeslot bufferization: data from DIN is stored in an input buffer and data from an

output buffer is played on DOUT. When the number of samples stored/played

reaches the buffer size, the processor is interrupted in order to read the input

buffer and prepare a new output buffer (or a DMA request is generated).

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