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SPEAR300 数据表(PDF) 78 Page - STMicroelectronics |
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SPEAR300 数据表(HTML) 78 Page - STMicroelectronics |
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78 / 83 page  Timing requirements SPEAr300 78/83 Doc ID 16324 Rev 2 Figure 44. SPI master mode external timing (clock phase = 1) 6.8 UART (Universal asynchronous receiver/transmitter) Figure 45. UART transmit and receive timings 10 td(ENL- CLKH/L) Delay time, SSP_CSn (output) falling edge to first SSP_CLK (output) rising or falling edge Tns 11 td(CLKH/L- ENH) Delay time, SSP_CLK (output) rising or falling edge to SSP_CSn (output) rising edge T/2 ns Table 48. Switching characteristics over recommended operating conditions for SPI master mode (clock phase = 1 ) (continued) No. Parameters Min Max Unit SSP_CSn SSP_SCLK (Clock Polarity = 0) SSP_SCLK (Clock Polarity = 1) SSP_MISO (Input) SSP_MOSI (Output) |
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