SPEAR300 datasheet(13/83 Pages) STMICROELECTRONICS

13 / 83 page

SPEAr300

Architecture overview

Doc ID 16324 Rev 2

13/83

Figure 3.

Clock generator overview

The multi clock generator block, takes a reference signal (which is usually delivered by the

PLL), generates all clocks for the IPs of SPEAr300 according to dedicated programmable

registers.

Each PLL uses an oscillator input of 24 MHz to generate a clock signal at a frequency

corresponding to the highest of the group. This is the reference signal used by the multi

clock generator block to obtain all the other required clocks for the group. Its main feature is

electromagnetic interference reduction capability.

The user can set up the PLL in order to modulate the VCO with a triangular wave. The

resulting signal has a spectrum (and power) spread over a small programmable range of

frequencies centered on F0 (the VCO frequency), obtaining minimum electromagnetic

emissions. This method replaces all the other traditional methods of EMI reduction, such as

filtering, ferrite beads, chokes, adding power layers and ground planes to PCBs, metal

shielding and so on. This gives the customer appreciable cost savings.

In sleep mode the SPEAr300 runs with the PLL disabled so the available frequency is 24

MHz or a sub-multiple (/2, /4, /8).

2.2.2

Power saving system mode control

Using three mode control bits, the system controller switch the SPEAr300 to any one of four

different modes: DOZE, SLEEP, SLOW and NORMAL.

●

SLEEP mode: In this mode the system clocks, HCLK and CPU_CLK, are disabled and

the System Controller clock is driven by a low speed oscillator (nominally 32768 Hz).

When either a FIQ or an IRQ interrupt is generated (through the VIC) the system enters

PLL1

DIV 2

PLL2

PLL3

DIV 4

HCLK

CPU_CLK

PCLK

DDR_CLK

CLK12MHZ

CLK30MHZ

CLK48MHZ

83 MHz

333 MHz

166 MHz

OSC

RTC

CLK32MHZ

32.768 kHz

24 MHz

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