SPEAR300 datasheet(35/83 Pages) STMICROELECTRONICS

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SPEAr300

Pin description

Doc ID 16324 Rev 2

35/83

3.3

Shared I/O pins (PL_GPIOs)

SPEAr300 devices feature, in the Reconfigurable Array Subsystem (RAS), specific sets of

IPs as well as groups of software controllable GPIOs (that can be used alternatively). In the

SPEAr300 the following IPs are implemented in the RAS:

●

FSMC NAND/NOR Flash interface

●

GPIO/Keyboard controller

●

8-bit camera interface

●

CLCD controller interface

●

Digital-to-analog converter (DAC)

●

I2S

●

4 SPI/I2C control signals

●

TDM block

●

SDIO interface

●

GPIOs

The 98 PL_GPIO and 4 PL_CLK pins have the following characteristics:

–

Output buffer: TTL 3.3 V capable up to 10 mA

–

Input buffer: TTL, 3.3 V tolerant, selectable internal pull up/pull down (PU/PD)

The PL_GPIOs can be configured in 13 different modes. This allows SPEAr300 to be

tailored for use in various applications, see Section 3.3.2.

3.3.1

PL_GPIO pin description

3.3.2

Configuration modes

This section describes the main operating modes created by using a selection of the

embedded IPs.

13 configurations are available selected by RAS register 2. The peripherals available in each

configuration are shown in Table 10: Available peripherals in each configuration mode

Details of each PL_GPIO pin are given for each mode in Table 11: PL_GPIO multiplexing

scheme.

Table 9.

PL_GPIO pin description

Group

Signal name

Ball

Direction

Function

Pin type

PL_GPIOs

PL_GPIO_97...

PL_GPIO_0

(see Table 11)I/O

General

purpose I/O or

multiplexed pins

(see Table 11)

(see the

introduction of

the Section 3.3

above)

PL_CLK1...

PL_CLK4

Programmable

logic external

clocks

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