AD6622SSLASHPCB datasheet(18/28 Pages) AD

18 / 28 page

AD6622

–18–

REV. 0

Start refers to the start-up of an individual channel, chip, or

multiple chips. If a channel is not used, it should be put in the

Sleep Mode to reduce power dissipation. Following a hard reset

(low pulse on the AD6622

RESET pin), all channels are placed

in the Sleep Mode.

NCO

FREQUENCY

NCO

NCO PHASE

ACCUMULATOR

HOP

HOLD-OFF

COUNTER

C = 1

C = 0

ENA

START

HOLD-OFF

START

COUNTER

C = 1

C = 0

ENA

START SYNC

SET

SLEEP

CLK

RESET

HOP SYNC

EXTERNAL

ADDRESS 4

ENA

Figure 20. NCO Shadow Register and Hold-Off Counter

Start with No Sync

If no synchronization is needed to start multiple channels or

multiple AD6622s, the following method can be used to ini-

tialize the device.

1. To program a channel, it must ﬁrst be set to the Program

Mode (bit high) and Sleep Mode (bit high) (External Address

4). The Program Mode allows programming of data memory

and coefﬁcient memory (all other registers are programmable

whether or not in Program Mode). Since no synchronization

is used all sync bits are set low (External Address 5). All

appropriate control and memory registers (ﬁlter) are then

loaded. The Start Update Hold-Off Counter (0x00) should

be set to 0.

2. Set the appropriate program and sleep bits low (External

Address 4). This enables the channel. The channel must have

Program and Sleep Mode low to activate a channel.

Start with Soft Sync

The AD6622 includes the ability to synchronize channels or chips

under microprocessor control. One action to synchronize is the

start of channels or chips. The Start Update Hold-Off Counter

(0x00) in conjunction with the start bit and sync bit (External

Address 5) allow this synchronization. Basically the Start Update

Hold-Off Counter delays the start of a channel(s) by its value

(number of AD6622 CLKs). The following method is used to

synchronize the start of multiple channels via microprocessor

control.

1. Set the appropriate channels to sleep mode (a hard reset

to the AD6622

RESET pin brings all four channels up in

sleep mode).

2. Write the Start Update Hold-Off Counter(s) (0x00) to the

appropriate value (greater than 1 and less than 2

16–1). If the

chip(s) is not initialized, all other registers should be loaded

at this step.

3. Write the Start bit and the SyncX(s) bit high (External

Address 5).

4. This starts the Start Update Hold-Off Counter counting

down. The counter is clocked with the AD6622 CLK signal.

When it reaches a count of one the Sleep bit of the appropri-

ate channel(s) is set low to activate the channel(s).

Start with Pin Sync

A sync pin is provided on the AD6622 to provide the most

accurate synchronization, especially between multiple AD6622s.

Synchronization of start with an external signal is accomplished

with the following method.

1. Set the appropriate channels to sleep mode (a hard reset to

the AD6622

RESET pin brings all four channels up in

sleep mode).

2. Write the Start Update Hold-Off Counter(s) (0x00) to the

appropriate value (greater than 1 and less than 2

16–1). If the

chip(s) is not initialized, all other registers should be loaded

at this step.

3. Set the start on pin sync bit and the appropriate sync pin

enable high (0x001).

4. When the sync pin is sampled high by the AD6622 CLK, it

enables the countdown of the Start Update Hold-Off Counter.

The counter is clocked with the AD6622 CLK signal. When

it reaches a count of one, the sleep bit of the appropriate

channel(s) is set low to activate the channel(s).

Hop is a jump from one NCO frequency to a new NCO frequency.

This change in frequency can be synchronized via microproces-

sor control or an external sync signal as described below.

To set the NCO frequency without synchronization the follow-

ing method should be used.

Set Freq No Hop

1. Set the NCO Freq Hold-Off Counter to 0.

2. Load the appropriate NCO frequency. The new frequency

will immediately be loaded to the NCO.

Hop with Soft Sync

The AD6622 includes the ability to synchronize a change in

NCO frequency of multiple channels or chips under micro-

processor control. The NCO Freq Hold-Off Counter (0x03), in

conjunction with the hop bit and the sync bit (Ext Address 5),

allow this synchronization. Basically the NCO Freq Hold-Off

Counter delays the new frequency from being loaded into the

NCO by its value (number of AD6622 CLKs). The following

method is used to synchronize a hop in frequency of multiple chan-

nels via microprocessor control.

AD6622S/PCB 数据表(PDF) 18 Page - Analog Devices

AD6622S/PCB 数据表(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载