AD6622SSLASHPCB datasheet(21/28 Pages) AD

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AD6622

–21–

REV. 0

Microport Control

All accesses to the internal registers and memory of the AD6622

are accomplished indirectly through the use of the microproces-

sor port external registers shown in Table XII. Accesses to the

External Registers are accomplished through the 3-bit address

bus (A[2:0]) and the 8-bit data bus (D[7:0]) of the AD6622

(Microport). External Address [3:0] provides access to data read

from or written to the internal memory (up to 32 bits). External

Address [0] is the least signiﬁcant byte and External Address [3]

is the most signiﬁcant byte. External Address [4] controls the

resets of each channel. External Address [5] controls the sync

status of each channel. External Address [7:6] determines the

Internal Address selected and whether this address is incremented

after subsequent reads and/or writes to the internal registers.

EXTERNAL MEMORY MAP

The External Memory Map is used to gain access to the Inter-

nal Memory Map described below. External Address [7:6] sets

the Internal Address to which subsequent reads or writes will

be performed. The top two bits of External Address [7] allow

the user to set the address to autoincrement after reads, writes,

or both. All internal data words have widths that are less than

or equal to 32 bits. Accesses to External Address [0] trigger

accesses to the AD6622’s internal memory map. Thus during

writes to the internal registers, External Address [0] must be

written last to ensure all data is transferred. Reads are the oppo-

site in that External Address [0] must be the ﬁrst data register

read (after setting the appropriate internal address) to initiate an

internal access.

External Address [5:4] reads and writes are immediately trans-

ferred to internal control registers. External Address [4] is the

reset register. The reset bits can be set collectively by the address.

The reset bits can be cleared by operation of start syncs (described

below).

External Address [5] is the sync register. These bits are write

only. There are three types of syncs: start, hop, and beam. Each

of these can be sent to any or all of the four channels. For example,

a write of X0010100 would issue a start sync to Channel C

only. A write of X1101111 would issue a beam sync and a hop

sync to all channels.

The internal address bus is 11 bits wide and the internal data

bus is 32 bits wide. External Address 7 is the Chan (Channel)

and stores the upper three bits of the address space in Chan[2:0].

Chan[7:6] deﬁne the autoincrement feature. If Bit 6 is high, the

internal address in incremented after an internal read. If Bit 7 is

high, the internal address is incremented after an internal write.

If both bits are high, the internal address in incremented after

either a write or a read. This feature is designed for sequential

access to internal locations. External Address 6 is the Addr

(Address) and stores the lower eight bits of the internal address.

External Addresses 3 through 0 store the 32 bits of the internal

data. All internal accesses are two clock cycles long.

Writing to an internal location with a data width of 16 bits is

achieved by ﬁrst writing the upper three bits of the address to

Bits 2 through 0 of the Chan. (Bits 7 and 6 of the Chan are

written to determine whether or not the auto increment fea-

ture is enabled.) The Addr is then written with the lower eight

bits of the internal address (it does not matter if the Addr is

written before the Chan as long as both are written before the

internal access). Since the data width of the internal address is

16 bits, only Data Register 1 and Data Register 0 are needed.

Data Register 1 must be written ﬁrst because the write to Data

always be the last register written to initiate the internal write.

Reading from the Microport is accomplished in a similar manner.

The internal address is ﬁrst written. A read from Data Register

0 activates the internal read, thus register 0 must always be read

ﬁrst to initiate an internal read. This provides the 8 LSBs of the

internal read through the Microport (D[7:0]). Additional bytes

are then read by changing the external address (A[2:0]) and

performing additional reads. If Data Register 3 (or any other)

is read before Data Register 0, incorrect data will be read. Data

core memory to the external memory locations. Once data register

is read, the remaining locations may be examined in any order.

The Microport of the AD6622 allows for multiple accesses

while

CS is held low (CS can be tied permanently low if the

Microport is not shared with additional devices). The user can

access multiple locations by pulsing the

WR or RD line and

changing the contents of the external 3-bit address bus. Access

to the external registers of Table XII is accomplished in one

of two modes using the

CS, RD, WR, and MODE inputs. The

access modes are Intel Nonmultiplexed Mode and Motorola

Nonmultiplexed Mode. These modes are controlled by the

MODE input (MODE = 0 for INM, MODE = 1 for MNM).

CS, RD, and WR control the access type for each mode.

Intel Nonmultiplexed Mode (INM)

MODE must be tied low to operate the AD6622 Microport

in INM Mode. The access type is controlled by the user with

the

CS, RD (DS), and WR (R/W) inputs. The RDY (DTACK)

signal is produced by the Microport to communicate to the

user the Microport is ready for an access. RDY (

DTACK) goes

low at the start of the access and is released when the internal

cycle is complete. See the timing diagrams for both the read and

write modes in the speciﬁcations.

Motorola Nonmultiplexed Mode (MNM)

MODE must be tied high to operate the AD6622 microprocessor

in MNM mode. The access type is controlled by the user with

the

CS, DS (RD), and R/W (WR) inputs. The DTACK (RDY)

signal is produced by the Microport to acknowledge the comple-

tion of an access to the user.

DTACK (RDY) goes low when an

internal access is complete and then will return high after

(

RD) is deasserted. See the timing diagrams for both the read

and write modes in the Speciﬁcations.

The

DTACK pin is conﬁgured as an open drain so that multiple

devices may be tied together at the microprocessor/microcontroller

without contention.

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