AD6622SSLASHPCB datasheet(20/28 Pages) AD

20 / 28 page

AD6622

–20–

REV. 0

SCALING

Proper scaling of the wideband output is critical to maximize the

spurious and noise performance of the AD6622. A relatively small

overflow anywhere in the data path can cause the spurious free

dynamic range to drop precipitously. Scaling down the output

levels also reduces dynamic range relative to an approximately

constant noise floor. A well-balanced scaling plan at each point

in the signal path will be rewarded with optimum performance.

The scaling plan can be separated into two parts: multicarrier

scaling and single-carrier scaling.

Multicarrier Scaling

An arbitrary number of AD6622s can be cascaded to create a

composite digital IF with many carriers. As the number of carriers

increases, the peak-to-rms ratio of the composite digital IF will

increase as well. It is possible and beneﬁcial to limit the peak-to-

rms ratio through careful frequency planning and controlled phase

offsets. Nevertheless, in most cases with a large number of carriers,

the worst-case peak is an unlikely event.

The AD6622 immediately preceding the DAC can be programmed

to clip rather than wrap around (see the Summation Block descrip-

tion). For a large number of carriers, a rare but ﬁnite chance

of clipping at the AD6622 wideband output will result in superior

dynamic range compared to lowering each carrier level until

clipping is impossible. This will also be the case for most DACs.

Through analysis or experimentation, an optimal output level of

individual carriers can be determined for any particular DAC.

Single-Carrier Scaling

Once the optimal power level is determined for each carrier, one

must determine the best way to achieve that level. The maximum

SNR can be achieved by maximizing the intermediate power

level at each processing stage. This can be done by assuming the

proper level at the output and working backwards along the signal

path: Summation, NCO, CIC, and ﬁnally, RCF.

The summation block is intended to combine multiple carriers,

with each carrier at least 6 dB below full scale. For this conﬁgu-

ration, the AD6622 driving the DAC should have clip detection

enable. OUT17 becomes a clip indicator that reports clipping in

both polarities. If the DAC requires offset binary outputs, the

internal offset binary conversion should be enabled as well. Any

preceding cascaded AD6622s should disable clip detection and

offset binary conversion. The IN17–IN0 of the ﬁrst AD6622 in the

cascade should be grounded. See the Summation Block section

for details. In this conﬁguration, intermediate OUT17s will

serve as guard bits that allow intermediate sums to exceed full

scale. As long as the ﬁnal output does not exceed 6 dB over full

scale, the clip detector will perform correctly.

If a single carrier needs to exceed –6 dB full scale, hardwired

scaling can be accomplished according to the table below. This

is most useful when the AD6622 is processing a Single Wide-

band Carrier such as UMTS or CDMA 2000.

Table XI. Output Bit Scaling

Max Single-

Connect to

Clip

Offset Binary

Carrier Level

DAC MSB

Detect

Compensation

–12.04 dB

OUT17

N/A

Internal

–6.02 dB

OUT16

Internal

0 dB

OUT15

+Only

0x18000

+6.02 dB

OUT14

+Only

0x1C000

+12.04 dB

OUT13

+Only

0x1E000

+18.06 dB

OUT12

+Only

0x1F000

+24.08 dB

OUT11

+Only

0x1F800

The NCO/Tuner is equipped with an output scalar that ranges

from –6.02 dB to –24.08 dB below full scale, in 6.02 dB steps.

See the NCO/Tuner section for details. The best SNR will be

achieved by maximizing the input level to the NCO and using

the largest possible NCO attenuation. For example, to achieve

an output level –20 dB below full scale, one should set the CIC

output level to –1.94 dB below full scale and attenuate by

–18.06 dB in the NCO.

The CIC is equipped with an output scalar that ranges from

0 dB to –150.51 dB below full scale in 6.02 dB steps. This large

attenuation is necessary to compensate for the potentially large

gains associated with CIC interpolation. See the CIC section for

details. For example to achieve an output level of –1.94 dB below

full scale, with a CIC5 interpolation of 27 (114.51 dB gain) and

a CIC2 interpolation of 3 (9.54 dB gain), one should set the

CIC_Scale to 20 and the RCF output level to –5.59 dB below

full scale.

– .

–

– .

1 94

9 54

114 51

6 02

5 59

+×

(18)

The RCF is equipped with an output scalar that ranges from 0 dB

to –18.06 dB below full scale in 6.02 dB steps. This attenuation

can be used to compensate for ﬁlter gain in the RCF. For example,

if the desired RCF output is –5.59 dB and the maxim gain of the

RCF coefﬁcients is 11.04 dB, then the RCF_Coarse_Scale should

be set to two and the coefﬁcients should be scaled so that the

largest coefﬁcient is –4.59 dB below full scale. The largest pos-

sible gain of the RCF coefﬁcients is when the largest coefﬁcient

of the impulse response is normalized to one. This means that

all of the coefﬁcients are as large as possible so the sum of the

coefﬁcients are as large as possible. This maximum gain will

determine the RCF_Coarse_Scale, which should be used to

make the total RCF gain between 0 dB and –6.02 dB. After the

RCF_Coarse_Scale is chosen, the coefﬁcients can be rescaled, as

in the example, to set the total RCF gain to a desired level. See the

RCF section for additional information.

– .

–

– .

559

1104

602

4 59

+×

(19)

Finally, as described in the RCF section, there may be a worst-

case peak of a phase that is larger than the channel center gain. In

the preceding example, if the worst-case to channel center ratio

is larger than 4.59 dB (potentially overflowing the RCF), the

RCF_Coarse_Scale should be reduced by one and the CIC_Scale

should be increased by one. In the preceding example, if the worst-

case to channel center ratio is larger than 5.59 dB (potentially

overflowing the RCF and CIC), the RCF_Coarse_Scale should be

reduced by one and the NCO_Output_Scale should be increased

by one.

MICROPORT INTERFACE

The Microport interface is the communications port between the

AD6622 and the host controller. There are two modes of bus

operation: Intel Nonmultiplexed Mode (INM), and Motorola

Nonmultiplexed Mode (MNM), which is set by hard wiring the

MODE pin to either ground or supply. The mode is selected

based on the use of the Microport control lines (

DS or RD,

DTACK or RDY, R/W or WR) and the capabilities of the host

processor. See the timing diagrams for details on the operation of

both modes.

The External Memory Map provides data and address registers

to read and write the extensive control registers in the Internal

Memory Map. The control registers access global chip functions

and multiple control functions for each independent channel.

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