AD6622SSLASHPCB datasheet(24/28 Pages) AD

24 / 28 page

AD6622

–24–

REV. 0

(0x000) Summation Mode Control

Controls functions in the summation block of the AD6622. When

set high, Bit 0 causes the output data to be clipped (no wrap-

around) when overrange of the output occurs. When Bit 0 is low,

overrange will result in wraparound. When set low, Bit 1 formats

the output data as two's complement. Bit 1 set high will for-

mat output data as offset binary.

(0x001) Sync Mode Control

Bits 3–0 when high enable synchronization of these channels.

See the Synchronization section of the data sheet for detailed

explanation.

Channel Function Registers

The following registers are channel-speciﬁc. “0x” denotes that

these values are represented as hexadecimal numbers. “n” repre-

sents the speciﬁed channel. Valid channels are n = 1, 2, 3, and 4.

(0xn00) Start Update Hold-Off Counter

The Start Update Hold-Off Counter is used to synchronize start

up of AD6622 channels and can be used to synchronize multiple

chips. The Start Update Hold-Off Counter is clocked by the

AD6622 CLK (master clock). See the Synchronization section

of the data sheet for detailed explanation. If no synchronization

is required, this register should be set to 0.

(0xn01) NCO Control

Bit 1:0 set the NCO scaling per the Table XIV.

Table XIV. Control Scale

0x01 Bit 1

0x01 Bit 0

NCO Output Level

–6 dB

–12 dB

–18 dB

–24 dB

Bit 2, when high, clears the NCO phase accumulator to 0 on

either a Soft Sync or Pin Sync (see Synchronization for details).

Bit 3, when high, enables NCO phase dither.

Bit 4, when high, enables NCO amplitude dither.

Bits 7:5 are reserved and should be written low.

(0xn02) NCO Frequency

This register is a 32-bit unsigned integer that sets the NCO

Frequency. The NCO Frequency contains a shadow register for

synchronization purposes. The shadow can be read back directly,

the NCO Frequency cannot.

NCO

CLK

Frequency

channel

=×









232

(20)

(0xn03) NCO Frequency Update Hold-Off Counter

The Hold-Off Counter is used to synchronize the change of

NCO frequencies. See the Synchronization section of the data

sheet for detailed explanation. If no synchronization is required,

this register should be set to 0.

(0xn04) NCO Phase Offset

This register is a 16-bit unsigned integer that is added to the phase

accumulator of the NCO. This allows phase synchronization of

multiple channels of the AD6622(s). See the Synchronization

section of the data sheet for details. The NCO Phase Offset con-

tains a shadow register for synchronization purposes. The shadow

can be read back directly, the NCO Phase Offset cannot.

(0xn05) NCO Phase Offset Update Hold-Off Counter

The Hold-Off Counter is used to synchronize the change of NCO

phases. See the Synchronization section of the data sheet for

detailed explanation. If no synchronization is required, this

(0xn06) CIC Scale

Bits 5:0 set the CIC scaling per the equation below.

CIC Scale

ceil

CIC

(log (

))

=×

(21)

See CIC section of the data sheet for details. Bits 7:6 are reserved

and should be set to 0.

(0xn07) Reserved

This register is reserved and should be set to 0.

(0xn08) CIC2 Interpolation – 1

This register sets the interpolation rate for the CIC2 ﬁlter stage

(unsigned integer). The programmed value is the CIC2 Interpo-

lation – 1. Maximum interpolation is limited by the CIC scaling

available (See CIC section of the data sheet).

(0xn09) CIC5 Interpolation – 1

This register sets the interpolation rate for the CIC5 ﬁlter

stage (unsigned integer). The programmed value is the CIC5

Interpolation – 1. Maximum interpolation is limited by the CIC

scaling available (See CIC section of the data sheet).

(0xn0A) Number of RCF Coefﬁcients – 1

This register sets the number of RCF Coefﬁcients and is limited

to a maximum of 128. The programmed value is the number of

RCF Coefﬁcients – 1.

(0xn0B) RCF Coefﬁcient Offset

This register sets the offset for RCF Coefﬁcients and is normally

set to 0. It can be viewed as a pointer that selects the portion of

the CMEM used when computing the RCF ﬁlter. This allows

multiple ﬁlters to be stored in the coefﬁcient memory space,

selecting the appropriate ﬁlter by setting the offset.

(0xn0C) Channel Mode Control 1

Bits 3:0 set NRCF/LRCF-1.

Bits 5:4 set the channel input format as shown below.

Table XV. Filter Mode

Bit 5

Bit 4

Input Mode

FIR

Reserved

Bit 6 Reserved.

Bit 7 Reserved.

(0xn0D) Channel Mode Control 2

Bits 4:0 set the SCLKDIVIDER which determines the serial clock

frequency based on the following equation.

CLK

SCLK

DIVIDER

×+

()

(22)

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