AD6622

–23–

REV. 0

INTERNAL CONTROL REGISTERS AND ON-CHIP RAM

Listed below is the mapping of internal AD6622 registers.

Table XIII. Internal Memory Map

Address

Bit Width

Name

Notation

Description

Common Function Registers (Not Associated with a Particular Channel)

0x000

8

Summation MODE Control

0: Clip Wideband Output

1: Offset Binary Wideband Output

2: Reserved, Must Be Set High

3–7: Reserved, Should Be Set Low

0x001

8

Sync MODE Control

0: Ch. A Sync Pin Enable

1: Ch. B Sync Pin Enable

2: Ch. C Sync Pin Enable

3: Ch. D Sync Pin Enable

4: Start on Pin Sync

5: Hop on Pin Sync

6: Beam Steer on Pin Sync

7: First Sync Only

Channel Function Registers (0x1XX = Ch. A, 0x2XX = Ch. B, 0x3XX = Ch. C, 0x4XX = Ch. D )

0x100

16

Start Update Hold-Off Counter

Start Update Hold Off Counter

0x101

8

NCO Control

1-0: Ch. A NCO Output Scale

2: Ch. A NCO Clear Phase Accum on Sync

3: Ch. A NCO Phase Dither Enable

4: Ch. A NCO Amp Dither Enable

7–5: Reserved

0x102

32

NCO Frequency

Ch. A NCO Frequency Value

0x103

16

NCO Freq Hold Off

Ch. A NCO Frequency Update Hold-Off Ctr

0x104

16

NCO Phase Offset

Ch. A NCO Phase Offset

0x105

16

NCO Phase Hold Off

Ch. A NCO Phase Offset Update Hold-Off Ctr

0x106

8

CIC Scale

4–0: Ch. A CIC Scale

7–5: Reserved

0x107

8

Reserved

7–0: Reserved

0x108

8

CIC2 Interpolation-1

Ch. A CIC2 Interpolation Factor-1

0x109

8

CIC5 Interpolation-1

Ch. A CIC5 Interpolation Factor-1

0x10A

8

RCF Coefficient Count

7: Reserved

0x10B

8

RCF Coefficient Offset

6–0: Ch. A RCF Coefficient Offset

7: Reserved

0x10C

8

Channel MODE Control 1

5–4: Ch. A Input Format:

00 = FIR

6: Reserved

7: Reserved

0x10D

8

Channel MODE Control 2

4–0: Ch. A Serial Clock Divider

5: Ch. A Phase EQ Enable

7–6: Ch. A RCF Coarse Scale:

00 = 0 dB

01 = –6 dB

10 = –12 dB

11 = –18 dB

0x10E

16

15–0: Reserved

0x10F

16

15–0: Reserved

0x110

16

Reserved

Reserved

0x111

16

Reserved

Reserved

0x112–0x11F

Reserved

Reserved

0x120–0x13F

16

Data Memory

Ch. A Data Memory

0x140–0x17F

16

Reserved

Reserved

0x180–0x1FF

16

Coefficient Memory

Ch. A Coefficient Memory

Additional Channels

0x200–0x2FF

Various

Channel B

Ch. B Registers (Organized as Ch. A Above)

0x300–0x3FF

Various

Channel C

Ch. C Registers (Organized as Ch. A Above)

0x400-0x4FF

Various

Channel D

Ch. D Registers (Organized as Ch. A Above)