ACT7000SC datasheet(4/25 Pages) AEROFLEX

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SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700

long latency floating-point operations can result in

there being even more instructions in process than

what is shown.

Note

that

instruction

dependencies,

resource

conflicts, and branches result in some of the

instruction slots being occupied by NOPs.

Integer Unit

Like the ACT 52xx family, the

ACT 7000SC

implements the MIPS IV Instruction Set Architecture,

and is therefore fully upward

compatible with

applications that run on processors such as the

R4650

and

R4700

that implement the

earlier

generation MIPS III Instruction Set Architecture.

Additionally,

the

ACT 7000SC

includes

two

implementation specific instructions not found in the

baseline MIPS IV ISA, but that are useful in the

embedded market place. Described in detail in a later

section of this datasheet, these instructions are

integer

multiply-accumulate

and

three-operand

integer multiply.

The ACT 7000SC integer unit includes thirty-two

general purpose 64-bit registers, the HI/LO result

registers

for

the

two-Pipeline

operand

integer

multiply/divide operations, and the program counter,

or PC. There are two separate execution units, one of

which can execute function, or F, type instructions

and one which can execute memory, or M, type

instructions. See above for a description of the

instruction types and the issue rules. As a special

case, integer multiply/divide instructions as well as

their corresponding MFHi and MFLo instructions can

only be executed in the F type execution unit. Within

each execution unit the operational characteristics

are the same as on previous QED designs with single

cycle ALU operations (add, sub, logical, shift), one

cycle load delay, and an autonomous multiply/divide

unit.

The ACT 7000SC has thirty-two general purpose

registers with register location (r0) hard wired to zero

value. These registers are used for scalar integer

operations and address calculation. In order to

service the two integer execution units, the register

file has four read ports and two write ports and is fully

bypassed both within and between the two execution

units to minimize operation latency in the pipeline.

ALU

The ACT 7000SC has two complete integer ALU’s

each consisting of an integer adder/subtractor, a logic

unit, and a shifter. Table 3 shows the functions

performed by the ALU’s for each execution unit. Each

of these units is optimized to perform all operations in

a single processor cycle.

Integer Multiply/Divide

The ACT 7000SC has a single dedicated integer

multiply/divide unit optimized for high-speed multiply

and

multiply-accumulate

operations.

The

multiply/divide unit resides in the F type execution

unit.

Table

shows the

performance

the

multiply/divide unit on each operation.

The baseline MIPS IV ISA specifies that the results

of a multiply or divide operation be placed in the Hi

and Lo registers. These values can then be

transferred to the general purpose register file using

the Move-from-Hi and Move-from-Lo (MFHI/MFLO)

instructions.

In addition to the baseline MIPS IV integer multiply

instructions, the ACT 7000SC also implements the

3-operand multiply instruction, MUL. This instruction

specifies that the multiply result go directly to the

integer register file rather than the Lo register. The

portion of the multiply that would have normally gone

into the Hi register is discarded. For applications

where it is known that the upper half of the multiply

result is not required, using the MUL instruction

eliminates the necessity of executing an explicit

MFLO instruction.

Also

included

the

ACT 7000SC

are

the

multiply-add

instructions

MAD/MADU.

This

instruction multiplies two operands and adds the

resulting product to the current contents of the Hi and

Lo registers. The multiply-accumulate operation is the

core

primitive

almost

all

signal

processing

algorithms allowing the ACT 7000SC to eliminate the

need for a separate DSP engine in many embedded

applications.

Table 3 – ALU Operations

Unit

F Pipe

M Pipe

Adder

add, sub

add, sub, data address

add

Logic

logic, moves, zero shifts

(nop)

logic, moves, zero shifts

(nop)

Shifter

non zero shift

non zero shift, store

align

Table 4 – Integer Multiply / Divide Operations

Opcode

Operand

Size

Latency

Repeat

Rate

Stall

Cycles

MULT/U,

MAD/U

16 bit

32 bit

MUL

16 bit

32 bit

DMULT,

DMULTU

any

980

DIV, DIVD

any

DDIV,

DDIVU

any

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