Aeroflex Circuit Technology

SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700

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For additional Detail Information regarding the operation of the Quantum Effect Devices (QED) RISCMark



RM7000

, 64-Bit Superscalar Microprocessor see the latest QED datasheet and users guide

(www.qedinc.com).

JTAG interface:

JTDI

Input

JTAG data in

JTAG serial data in.

JTCK

Input

JTAG clock input

JTAG serial clock input.

JTDO

Output

JTAG data out

JTAG serial data out.

JTMS

Input

JTAG command

JTAG command signal, signals that the incoming serial data is command data.

Initialization Interface:

BigEndian

Input

Big Endian / Little Endian Control

Allows the system to change the processor addressing mode without rewriting

the mode ROM.

VccOK

Input

Vcc is OK

When asserted, this signal indicates to the ACT 7000 that the 2.5V power supply

has been above 2.25V for more than 100 milliseconds and will remain stable.

The assertion of VccOK initiates the reading of the boot-time mode control serial

stream.

ColdReset*

Input

Cold Reset

This signal must be asserted for a power on reset or a cold reset. ColdReset

must be de-asserted synchronously with SysClock.

Reset*

Input

Reset

This signal must be asserted for any reset sequence. It may be asserted

synchronously or asynchronously for a cold reset, or synchronously to initiate a

warm reset. Reset must be de-asserted synchronously with SysClock.

ModeClock

Output

Boot Mode Clock

Serial boot-mode data clock output at the system clock frequency divided by two

hundred and fifty six.

ModeIn

Input

Boot Mode Data In

Serial boot-mode data input.

Pin Descriptions (Cont.)

The following is a list of control, data, clock, interrupt, and miscellaneous pins of the ACT 7000SC.

Pin Name

Type

Description