ACT7000SC datasheet(15/25 Pages) AEROFLEX

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SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700

level registers are located in the coprocessor 0 control

space see the section describing coprocessor 0.

In addition to programmable priority levels, the ACT

7000SC also permits the spacing between interrupt

vectors to be programmed. For example, the

minimum spacing between two adjacent vectors is

0x20

while

the

maximum

0x200.

This

programmability allows the user to either set up the

vectors as jumps to the actual interrupt routines or, if

interrupt latency is paramount, to include the entire

interrupt routine at the vector. Table 15 illustrates the

complete set of vector spacing selections along with

the coding as required in the Interrupt Control register

bits 4:0.

In general, the active interrupt priority combined

with the spacing setting generates a vector offset

which is then added to the interrupt base address of

0x200 to generate the interrupt exception offset. This

offset is then added to the exception base to produce

the final interrupt vector address.

Standby Mode

The ACT 7000SC provides a means to reduce the

amount of power consumed by the internal core when

the CPU would not otherwise be performing any

useful operations. This state is known as Standby

Mode.

Executing the WAIT instruction enables interrupts

and enters Standby Mode. When the WAIT instruction

completes the W pipe stage, if the SysAD bus is

currently idle, the internal processor clocks will stop

thereby freezing the pipeline. The phase lock loop, or

PLL, internal timer/ counter, and the “wake up” input

pins:

IP[5:0]*,

NMI*,

ExtReq*,

Reset*,

and

ColdReset* continue to operate in their normal

fashion. If the SysAD bus is not idle when the WAIT

instruction completes the W pipe stage, then the

WAIT is treated as a NOP. Once the processor is in

Standby,

any

interrupt, including

the

internally

generated timer interrupt, will cause the processor to

exit Standby and resume operation where it left off.

The WAIT instruction is typically inserted in the idle

loop of the operating system or real time executive.

JTAG Interface

The

ACT

7000SC

interface

supports

JTAG

boundary scan in conformance with IEEE 1149.1. The

JTAG interface is especially helpful for checking the

integrity of the processor’s pin connections.

Boot-Time Options

Fundamental operational modes for the processor

are initialized by the boot-time mode control interface.

The boot-time mode control interface is a serial

interface

operating

very

low

frequency

(SysClock divided by 256). The low frequency

operation allows the initialization information to be

Table 15 – Interrupt Vector Spacing

ICR[4..0]

Spacing

0x0

0x000

0x1

0x020

0x2

0x040

0x4

0x080

0x8

0x100

0x10

0x200

others

reserved

Table 11 – Cause Register

29,28

23..8

6..2

0,1

IP[15..0]

EXC

Table 12 – Interupt Control Register

31..16

15..8

6..5

4..00

IM[15..8]

Spacing

Table 13 – IPLLO Register

31..28

27..24

23..20

19..16

15..12

11..8

7..4

3..0

IPL7

IIPL6

IPL5

IPL4

IPL3

IPL2

IPL1

IPL0

Table 14 – IPLHI Register

31..28

27..24

23..20

19..16

15..12

11..8

7..4

3..0

IPL13

IPL12

IPL11

IPL10

IPL9

IPL8

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