ACT7000SC datasheet(14/25 Pages) AEROFLEX

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SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700

The performance counter interrupt will only occur

when interrupts are enabled in the Status register,

IE=1, and Interrupt Mask bit 13 (IM[13]) of the

coprocessor 0 interrupt control register is not set.

Since the performance counter can be set up to

count clock cycles, it can be used as either a) a

second timer or b) a watchdog interrupt. A watchdog

interrupt can be used as an aid in debugging system

or software “hangs.” Typically the software is setup to

periodically update the count so that no interrupt will

occur. When a hang occurs the interrupt ultimately

triggers thereby breaking free from the hang-up.

Interrupt Handling

In order to provide better real time interrupt

handling, the ACT 7000SC provides an extended set

of hardware interrupts each of which can be

separately prioritized and separately vectored.

As described above, the performance counter is

also a hardware interrupt source, IP[13]. Also,

whereas the R4000 and R5000 family processors

map the timer interrupt onto IP[7], the ACT 7000SC

provides a separate interrupt, IP[12], for this purpose.

All of these interrupts, IP[13..0], the Performance

Counter, and the Timer, have corresponding interrupt

mask bits, IM[13..0], and interrupt pending bits,

IP[13..0], in the Status, Interrupt Control, and Cause

registers. The bit assignments for the Interrupt

Control and Cause registers are shown in Table 11

and Table 12 below. The Status register has not

changed from the RM5200 Family and R5000, and is

not shown.

The IV bit in the Cause register is the global enable

bit for the enhanced interrupt features. If this bit is

clear then interrupt operation is compatible with the

RM5200 Family and R5000. Although not related to

the interrupt mechanism, note that the W1 and W2

bits indicate which Watch register caused a particular

Watch exception.

In the Interrupt Control register, the interrupt vector

spacing is controlled by the Spacing field as

described below. The Interrupt Mask field (IM[15..8])

contains the interrupt mask for interrupts eight

through thirteen. IM[15..14] are reserved for future

use. The Timer Exclusive (TE) bit if set moves the

Timer interrupt to IP[12]. If clear, the Timer interrupt

will be or’ed into IP[7] as on the R5000.

The Interrupt Control register uses IM13 to enable

the Performance Counter Control.

Priority of the interrupts is set via two new

coprocessor 0 registers called Interrupt Priority Level

Lo, IPLLO, and Interrupt Priority Level Hi, IPLHI.

These

two

registers

contain

four-bit

field

corresponding to each interrupt thereby allowing each

interrupt to be programmed with a priority level from 0

to 13 inclusive. The priorities can be set in any

manner including having all the priorities set exactly

the same. Priority 0 is the highest level and priority 15

the lowest. The format of the priority level registers is

shown in Table 13 and Table 14 below. The priority

Table 10 – Performance Counter Control

PerfControl

Field

Description

4..0

Event Type

00: Clock cycles

01: Total instructions issued

02: Floating-point instructions issued

03: Integer instructions issued

04: Load instructions issued

05: Store instructions issued

06: Dual issued pairs

07: Branch prefetches

08: External Cache Misses

09: Stall cycles

0A: Secondary cache misses

0B: Instruction cache misses

0C: Data cache misses

0D: Data TLB misses

0E: Instruction TLB misses

0F: Joint TLB instruction misses

10: Joint TLB data misses

11: Branches taken

12: Branches issued

13: Secondary cache writebacks

14: Primary cache writebacks

15: Dcache miss stall cycles (cycles

where both cache miss tokens

taken and a third address is

requested)

16: Cache misses

17: FP possible exception cycles

18: Slip Cycles due to multiplier busy

19: Coprocessor 0 slip cycles

1A: Slip cycles due to pending

non-blockingloads

1B: Write buffer full stall cycles

1C: Cache instruction stall cycles

1D: Multiplier stall cycles

1E: Stall cycles due to pending

non-blocking loads - stall start of

exception

7..5

Reserved (must be zero)

Count in Kernel Mode

0: Disable

1: Enable

Count in User Mode

0: Disable

1: Enable

Count Enable

0: Disable

1: Enable

31..11

Reserved (must be zero)

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