ACT7000SC datasheet(10/25 Pages) AEROFLEX

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SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700

Cache Locking

The ACT 7000SC allows critical code or data

fragments to be locked into the primary and

secondary caches. The user has complete control

over what locking is performed with cache line

granularity. For instruction and data fragments in the

primaries, locking is accomplished by setting either or

both of the cache lock enable bits in the CP0 ECC

or a Fill_I cache operation for data or instructions

respectively. Only two sets are lockable within each

cache: set A and set B. Locking within the secondary

works identically to the primaries using a separate

secondary lock enable bit and the same set selection

field. As with the primaries, only two sets are lockable:

sets A and B. Table 7 summarizes the cache locking

capabilities.

Cache Management

To improve the performance of critical data

movement operations in the embedded environment,

the ACT 7000SC significantly improves the speed of

operation of certain critical cache management

operations as compared with the R5000 and R4000

families.

particular,

the

speed

the

Hit-Write-back-Invalidate and Hit-Invalidate cache

operations has been improved in some cases by an

order of magnitude over that of the earlier families.

Table 8 compares the ACT 7000SC with the R4000

and R5000 processors.

For the Hit-Dirty case of Hit-Writeback-Invalidate, if

the writeback buffer is full from some previous cache

eviction then n is the number of cycles required to

empty the write-back buffer. If the buffer is empty then

n is zero.

The penalty value is the number of processor

cycles beyond the one cycle required to issue the

instruction that is required to implement the operation.

Table 6 – Cache Attributes

Attribute

Instruction

Data

Secondary

Size

16KB

256KB

Associativity

4-way

Replacement Algorithm.

cyclic

Line size

32 byte

Index

vAddr 11..0

pAddr 15..0

Tag

pAddr 35..12

pAddr 35..16

Write policy

n.a.

write-back, write-through

block write-back, bypass

read policy

n.a.

non-blocking (2 outstanding) non-blocking (data only, 2

outstanding)

read order

critical word first

write order

sequential

miss restart following:

complete line

first double (if waiting for

data)

n.a.

Parity

per word

per byte

per doubleword

Table 7 – Cache Locking Control

Cache

Lock

Enable

Set Select

Activate

Primary I

ECC[27]

ECC[28]=

0→A

ECC[28]=

1→B

Fill_I

Primary D

ECC[26]

ECC[28]=

0→A

ECC[28]=

1→B

Load/Store

Secondary

ECC[25]

ECC[28]=

0→A

ECC[28]=

1→B

Fill_I or

Load/Store

Table 8 – Penalty Cycle

Operation

Condition

Penalty

ACT 7000S

R4000/R500

Hit-Writebac

k-Invalidate

Miss

Hit-Clean

Hit-Dirty

3+n

14+n

Hit-Invalidate Miss

Hit

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