ACT7000SC datasheet(6/25 Pages) AEROFLEX

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Aeroflex Circuit Technology

SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700

address translation buffer, or DTLB, a Joint TLB, or

JTLB, and coprocessor registers used by the virtual

memory mapping sub-system.

System Control Coprocessor Registers

The ACT 7000SC incorporates all system control

coprocessor

(CP0)

registers

internally.

These

registers provide the path through which the virtual

memory system’s page mapping is examined and

modified, exceptions are handled, and operating

modes

are

controlled

(kernel

vs.

user

mode,

interrupts enabled or disabled, cache features). In

addition, the ACT 7000SC includes registers to

implement a real-time cycle counting facility, to aid in

cache and system diagnostics, and to assist in data

error detection.

To support the non-blocking caches and enhanced

interrupt handling capabilities of the ACT 7000SC,

both the data and control register spaces of CP0 are

supported by the ACT 7000SC. In the data register

space, that is the space accessed using the MFC0

and MTC0 instructions, the ACT 7000SC supports the

same registers as found in the RM5200, R4000 and

R5000 families. In the control space, that is the space

accessed by the previously unused CTC0 and CFC0

instructions, the ACT 7000SC supports five new

registers. The first three of these new 32-bit registers

support the enhanced interrupt handling capabilities

and are the Interrupt Control, Interrupt Priority Level

Lo (IPLLO), and Interrupt Priority Level Hi (IPLHI)

registers. These registers are described further in the

section on interrupt handling. The other two registers,

Imprecise Error 1 and Imprecise Error 2, have been

added to help diagnose bus errors which occur on

non-blocking memory references.

Figure 4 shows the CP0 registers.

Virtual to Physical Address Mapping

The ACT 7000SC provides three modes of virtual

addressing:

• user mode

• supervisor mode

• kernel mode

This mechanism is available to system software to

provide a secure environment for user processes. Bits

in the CP0 Status register determine which virtual

addressing mode is used. In the user mode, the ACT

7000SC provides a single, uniform virtual address

space of 256GB (2GB in 32-bit mode).

When operating in the kernel mode, four distinct

virtual address spaces, totalling 1024GB (4GB in

32-bit mode), are simultaneously available and are

differentiated by the high-order bits of the virtual

address.

The ACT 7000SC processor also supports a

supervisor mode in which the virtual address space is

256.5GB (2.5GB in 32-bit mode), divided into three

regions based on the high-order bits of the virtual

address. Figure 5 shows the address space layout for

32-bit operation.

Info

Index

Random

Wired

PRid

15*

LLAddr

17*

TagLo

28*

TagHi

29*

EPC

14*

ECC

26*

Status

12*

Context

Count

BadVAddr

Compare

11*

Cause

13*

Watch1

18*

Watch2

19*

ErrorEPC

30*

Config

16*

Perf Counter

25*

Perf Ctr Cntrl

22*

Watch Mask

24*

IPLHI

19*

IPLLO

18*

IntControl

20*

Imp Error 1

26*

Imp Error 2

27*

PageMask

EntryHi

10*

EntryLo1

EntryLo0

TLB

(entries protected

from TLBWR)

Used for memory

management

* Registered number

Used for exception

processing

Control Space Registers

Xcontext

20*

CacheErr

27*

Figure 4 – CP0 Registers

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