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ACT7000SC 数据表(PDF) 20 Page - Aeroflex Circuit Technology |
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ACT7000SC 数据表(HTML) 20 Page - Aeroflex Circuit Technology |
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20 / 25 page ![]() Aeroflex Circuit Technology SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700 20 System Interface Parameters Parameter8 Sym Test Conditions 150MHz 200MHz 210MHz 225MHz Units Min Max Min Max Min Max Min Max Data Output2,3 tDO mode14...13 = 10 (fastest) 1.0 6.0 1.0 6.0 1.0 5.5 1.0 5.5 ns mode14...13 = 11 1.0 6.5 1.0 6.5 1.0 6.0 1.0 6.0 ns mode14...13 = 00 1.0 7.0 1.0 7.0 1.0 6.5 1.0 6.5 ns mode14...13 = 01 (slowest) 1.0 7.5 1.0 7.5 1.0 7.0 1.0 7.0 ns Data Setup4 tDS trise = see above table 2.52.5 2.52.5 ns Data Hold4 tDH tfall = see above table 1.01.0 1.01.0 ns Notes: 1. Timings are measured from 1.5V of the clock to 1.5V of the signal. 2. Capacitive load for all output timings is 50pF. 3. Data Output timing applies to all signal pins whether tristate I/O or output only. 4. Setup and Hold parameters apply to all signal pins whether tristate I/O or input only. Boot-Time Interface Parameters Parameter Symbol Test Conditions Min Max Units Mode Data Setup tDS 4 SysClock cycles Mode Data Hold tDH 0 SysClock cycles SysClock Timing Input Timing Output Timing ±tJitterIn tSCRise tSCFall SysClock tSCP Data SysClock Data tDH tDS Data SysClock Data Data tDO tDO MIN Clock Timing System Interface Timing (SysAD, SysCmd, ValidIn*, ValidOut*, etc.) |
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