ADE7763ARSZ datasheet(34/56 Pages) AD

34 / 56 page

ADE7763

Data Sheet

Rev. C | Page 34 of 56

Integration Times under Steady Load

As mentioned in the last section, the discrete time sample

period (T) for the accumulation register is 1.1 µs (4/CLKIN).

With full-scale sinusoidal signals on the analog inputs and the

VAGAIN register set to 0x000, the average word value from the

apparent power stage is 0xA D055. The maximum value that

can be stored in the apparent energy register before it overflows

is 224 or 0xFF FFFF. The average word value is added to the

internal register, which can store 248 or 0xFFFF FFFF FFFF

before it overflows. Therefore, the integration time under these

conditions with VADIV = 0 is calculated as follows:

min

888

0xAD055

FFFF

0xFFFF

Time

(28)

When VADIV is set to a value other than 0, the integration time

varies, as shown in Equation 29.

Time = TimeWDIV= 0 × VADIV

(29)

LINE APPARENT ENERGY ACCUMULATION

The ADE7763 is designed with a special apparent energy

accumulation mode, which simplifies the calibration process.

By using the on-chip zero-crossing detection, the ADE7763

accumulates the apparent power signal in the LVAENERGY

Figure 68. The line apparent energy accumulation mode is

always active.

The number of half line cycles is specified in the LINECYC

accumulate apparent power for up to 65,535 combined half

cycles. Because the apparent power is integrated on the same

integral number of line cycles as the line active energy register,

these two values can be easily compared. The active and apparent

energies are calculated more accurately because of this precise

timing control. At the end of an energy calibration cycle, the

CYCEND flag in the interrupt status register is set. If the

CYCEND mask bit in the interrupt mask register is enabled, the

IRQ output also will go active low. Thus, the IRQ line can also

be used to signal the end of a calibration.

The line apparent energy accumulation uses the same signal path

as the apparent energy accumulation. The LSB size of these two

registers is equivalent.

VADIV[7:0]

LPF1

LVAENERGY[23:0]

LVAENERGY REGISTER IS

UPDATED EVERY LINECYC

ZERO CROSSINGS WITH THE

TOTAL APPARENT ENERGY

DURING THAT DURATION

APPARENT

POWER

FROM

CHANNEL 2

ADC

LINECYC[15:0]

ZERO-CROSSING

DETECTION

CALIBRATION

CONTROL

Figure 68. Apparent Energy Calibration

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