ADE7763ARSZ datasheet(16/56 Pages) AD

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ADE7763

Data Sheet

Rev. C | Page 16 of 56

FREQUENCY (Hz)

102

103

–88.0

–88.5

–89.0

–89.5

–90.0

–90.5

Figure 29. Combined Phase Response of the

Digital Integrator and Phase Compensator

FREQUENCY (Hz)

–1.0

–6.0

–1.5

–2.0

–2.5

–3.5

–4.5

–5.5

–3.0

–4.0

–5.0

Figure 30. Combined Gain Response of the

Digital Integrator and Phase Compensator (40 Hz to 70 Hz)

–89.75

–89.80

–89.85

–89.90

–89.95

–90.00

FREQUENCY (Hz)

–90.05

–90.10

–89.70

Figure 31. Combined Phase Response of the

Digital Integrator and Phase Compensator (40 Hz to 70 Hz)

Note that the integrator has a –20 dB/dec attenuation and

approximately a –90° phase shift. When combined with a di/dt

sensor, the resulting magnitude and phase response should be a

flat gain over the frequency band of interest. The di/dt sensor

has a 20 dB/dec gain. It also generates significant high

frequency noise, necessitating a more effective antialiasing filter

to avoid noise due to aliasing—see the Antialias Filter section.

When the digital integrator is switched off, the ADE7763 can be

used directly with a conventional current sensor such as a current

transformer (CT) or with a low resistance current shunt.

ZERO-CROSSING DETECTION

The ADE7763 has a zero-crossing detection circuit on Channel 2.

This zero crossing is used to produce an external zero-crossing

signal (ZX), which is used in the calibration mode (see the

Calibrating an Energy Meter section). This signal is also used to

initiate a temperature measurement (see the Temperature

Measurement section).

Figure 32 shows how the zero-crossing signal is generated from

the output of LPF1.

1, 2, 1,

8, 16

ADC 2

REFERENCE

LPF1

f–3dB = 140Hz

–63%TO +63% FS

PGA2

{GAIN[7:5]}

V2P

V2N

ZERO

CROSSING

MULTIPLIER

2.32° @ 60Hz

1.0

0.93

LPF1

Figure 32. Zero-Crossing Detection on Channel 2

The ZX signal goes logic high upon a positive-going zero

crossing and logic low upon a negative-going zero crossing on

Channel 2. The ZX signal is generated from the output of LPF1.

LPF1 has a single pole at 140 Hz (@ CLKIN = 3.579545 MHz).

As a result, there is a phase lag between the analog input signal

V2 and the output of LPF1. The phase response of this filter is

shown in the Channel 2 Sampling section. The phase lag response

of LPF1 results in a time delay of approximately 1.14 ms

(@ 60 Hz) between the zero crossing on the analog inputs of

Channel 2 and the rising or falling edge of ZX.

Zero-crossing detection also drives the ZX flag in the interrupt

status register. The ZX flag is set to Logic 1 on the rising and

falling edge of the voltage waveform. It remains high until the

status register is read with reset. An active low in the IRQ

output appears if the corresponding bit in the interrupt enable

The flag in the interrupt status register and the IRQ output are

set to their default values when reset (RSTSTATUS) is read in

the interrupt status register.

Zero-Crossing Timeout

Zero-crossing detection has an associated timeout register,

ZXTOUT. This unsigned, 12-bit register is decremented (1 LSB)

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