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Data Sheet

ADE7763

Rev. C | Page 9 of 56

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V2N

V2P

AGND

REFIN/OUT 9

DGND 10

CLKIN

IRQ

SAG

ADE7763

TOP VIEW

(Not to Scale)

DVDD

AVDD

V1P

V1N

DOUT

SCLK

CLKOUT

RESET

DIN

Figure 5. Pin Configuration (SSOP Package)

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

RESET

Reset Pin1. A logic low on this pin holds the ADCs and digital circuitry (including the serial interface) in a

reset condition.

DVDD

Digital Power Supply. This pin provides the supply voltage for the digital circuitry. The supply voltage

should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to DGND with a

10 µF capacitor in parallel with a ceramic 100 nF capacitor.

AVDD

Analog Power Supply. This pin provides the supply voltage for the analog circuitry. The supply should be

maintained at 5 V ± 5% for specified operation. Minimize power supply ripple and noise at this pin by using

proper decoupling. The typical performance graphs show the power supply rejection performance. This

pin should be decoupled to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.

4, 5

V1P, V1N

Analog Inputs for Channel 1. This channel is intended for use with a di/dt current transducer, i.e., a

Rogowski coil or another current sensor such as a shunt or current transformer (CT). These inputs are fully

differential voltage inputs with maximum differential input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V,

depending on the full-scale selection—see the Analog Inputs section. Channel 1 also has a PGA with gain

selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±0.5 V. Both

inputs have internal ESD protection circuitry and can sustain an overvoltage of ±6 V without risk of

permanent damage.

6, 7

V2N, V2P

Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These inputs are

fully differential voltage inputs with a maximum differential signal level of ±0.5 V. Channel 2 also has a PGA

with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is

±0.5 V. Both inputs have internal ESD protection circuitry and can sustain an overvoltage of ±6 V without

risk of permanent damage.

AGND

Analog Ground Reference. This pin provides the ground reference for the analog circuitry, i.e., ADCs and

reference. This pin should be tied to the analog ground plane or to the quietest ground reference in the

system. Use this quiet ground reference for all analog circuitry, such as antialiasing filters and current and

voltage transducers. To minimize ground noise around the ADE7763, connect the quiet ground plane

to the digital ground plane at only one point. It is acceptable to place the entire device on the analog

ground plane.

REFIN/OUT

Access to the On-Chip Voltage Reference. The on-chip reference has a nominal value of 2.4 V ± 8% and a

typical temperature coefficient of 30 ppm/°C. An external reference source can also be connected at this

pin. In either case, this pin should be decoupled to AGND with a 10 µF capacitor in parallel with a 100nF

ceramic capacitor.

DGND

Digital Ground Reference. This pin provides the ground reference for the digital circuitry, i.e., multiplier,

filters, and digital-to-frequency converter. Because the digital return currents in the ADE7763 are small, it is

acceptable to connect this pin to the analog ground plane of the system. However, high bus capacitance

on the DOUT pin could result in noisy digital current, which could affect performance.

Calibration Frequency Logic Output. The CF logic output gives active power information. This output is

intended to be used for operational and calibration purposes. The full-scale output frequency can be

adjusted by writing to the CFDEN and CFNUM registers—see the Energy-to-Frequency Conversion section.

Voltage Waveform (Channel 2) Zero-Crossing Output. This output toggles logic high and logic low at the

zero crossing of the differential signal on Channel 2—see the Zero-Crossing Detection section.

SAG

This open-drain logic output goes active low when either no zero crossings are detected or a low voltage

threshold (Channel 2) is crossed for a specified duration—see the Line Voltage Sag Detection section.

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