ADE7763ARSZ datasheet(48/56 Pages) AD

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ADE7763

Data Sheet

Rev. C | Page 48 of 56

REGISTERS

Table 9. Summary of Registers by Address

Address

Name

R/W

No. Bits

Default

Type1

Description

0x01

WAVEFORM

0x0

Waveform Register. When WSMP (Bit 3) in the interrupt enable register is

set to 1, this read-only register contains the sampled waveform data from

either Channel 1, Channel 2, or the active power signal. The data source

and the length of the waveform registers are selected by Bits 14 and 13 in

the mode register—see the Channel 1 Sampling and Channel 2 Sampling

sections.

0x02

AENERGY

0x0

Active Energy Register. Active power is accumulated (integrated) over

time in this 24-bit, read-only register—see the Energy Calculation

section.

0x03

RAENERGY

0x0

Same as the active energy register, except that the register is reset to 0

following a read operation.

0x04

LAENERGY

0x0

Line Accumulation Active Energy Register. The instantaneous active

power is accumulated in this read-only register over the LINECYC number

of half line cycles.

0x05

VAENERGY

0x0

Apparent Energy Register. Apparent power is accumulated over time in

this read-only register.

0x06

RVAENERGY

0x0

Same as the VAENERGY register, except that the register is reset to 0

following a read operation.

0x07

LVAENERGY

0x0

Line Accumulation Apparent Energy Register. The instantaneous real

power is accumulated in this read-only register over the LINECYC number

of half line cycles.

0x08

RESERVED

0x09

MODE

R/W

0x000C

Mode Register. This is a 16-bit register through which most of the

ADE7763’s functionality is accessed. Signal sample rates, filter enabling,

and calibration modes are selected by writing to this register. The

contents can be read at any time—see the Mode Register (0X09) section.

0x0A

IRQEN

R/W

0x40

Interrupt Enable Register. ADE7763 interrupts can be deactivated at any

time by setting the corresponding bit in this 16-bit enable register to

Logic 0. The status register continues to detect an interrupt event even if

disabled; however, the IRQ output is not activated—see the Interrupts

section.

0x0B

STATUS

0x0

Interrupt Status Register. This is a 16-bit read-only register that contains

information regarding the source of ADE7763 interrupts—see the

Interrupts section.

0x0C

RSTSTATUS

0x0

Same as the interrupt status register, except that the register contents are

reset to 0 (all flags cleared) after a read operation.

0x0D

CH1OS

R/W

0x00

Channel 1 Offset Adjust. Bit 6 is not used. Writing to Bits 0 to 5 allows

offsets on Channel 1 to be removed—see the Analog Inputs and CH1OS

digital integrator on Channel 1; writing Logic 0 disables the integrator.

The default value of this bit is 0.

0x0E

CH2OS

R/W

0x0

Channel 2 Offset Adjust. Bits 6 and 7 are not used. Writing to Bits 0 to 5 of

this register allows offsets on Channel 2 to be removed—see the Analog

Inputs section. Note that the CH2OS register is inverted. To apply a

positive offset, a negative number is written to this register.

0x0F

GAIN

R/W

0x0

PGA Gain Adjust. This 8-bit register is used to adjust the gain selection for

the PGA in Channels 1 and 2—see the Analog Inputs section.

0x10

PHCAL

R/W

0x0D

Phase Calibration Register. The phase relationship between Channel 1

and 2 can be adjusted by writing to this 6-bit register. The valid content

of this twos complement register is between 0x1D to 0x21. At the line

frequency of 60 Hz, this ranges from –2.06° to +0.7°—see the Phase

Compensation section.

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