SL40307A-R19KHF datasheet(22/53 Pages) IRF

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IR3846

22 www.irf.com

August 01, 2013

(< VCC-1.5V)

RSA

RS+

RS-

RSo

Vout

Resistor Divider

Figure 12: General Remote Sense Configuration

Figure 13: Remote Sense Configuration for Vout less

than VCC-1.5V

EXTERNAL SYNCHRONIZATION

IR3846 incorporates an internal phase lock loop (PLL)

circuit which enables synchronization of the internal

oscillator to an external clock. This function is

important to avoid sub-harmonic oscillations due to

beat frequency for embedded systems when multiple

point-of-load (POL) regulators are used. A multi-

function pin, Rt/Sync, is used to connect the external

clock. If the external clock is present before the

converter turns on, Rt/Sync pin can be connected to

the external clock signal solely and no other resistor is

needed. If the external clock is applied after the

converter turns on, or the converter switching

frequency needs to toggle between the external clock

frequency and the internal free-running frequency, an

external resistor from Rt/Sync pin to LGnd is required

to set the free-running frequency.

When an external clock is applied to Rt/Sync pin after

the converter runs in steady state with its free-running

frequency,

transition

from

the

free-running

frequency to the external clock frequency will happen.

This transition is to gradually make the actual

switching frequency equal to the external clock

frequency, no matter which one is higher. When the

external clock signal is removed from Rt/Sync pin, the

switching frequency is also changed to free-running

gradually. In order to minimize the impact from these

transitions to output voltage, a diode is recommended

to add between the external clock and Rt/Sync pin.

Figure 14 shows the timing diagram of these

transitions.

An internal circuit is used to change the PWM ramp

slope according to the clock frequency applied on

Rt/Sync pin. Even though the frequency of the

external synchronization clock can vary in a wide

range, the PLL circuit keeps the ramp amplitude

constant, requiring no adjustment of the loop

compensation. PVin variation also affects the ramp

amplitude, which will be discussed separately in Feed-

Forward section.

SYNC

...

Graduallychange

Fs1

Fs2

Fs1

FreeRunning

Frequency

Synchronizetothe

external clock

Returntofree-

runningfreq

Graduallychange

Figure 14: Timing Diagram for Synchronization

to the external clock (Fs1>Fs2 or Fs1<Fs2)

FEED-FORWARD

Feed-Forward (F.F.) is an important feature, because

it can keep the converter stable and preserve its load

transient performance when PVin varies. The PWM

ramp amplitude (Vramp) is proportionally changed

with PVin to maintain PVin/Vramp almost constant

throughout PVin variation range (as shown in Figure

15). The PWM ramp amplitude is adjusted to 0.15 of

PVin. Thus, the control loop bandwidth and phase

margin can be maintained constant. Feed-forward

function can also minimize impact on output voltage

from fast PVin change. F.F. is disabled when

PVin<6.2V and the PWM ramp is typically 0.9V. For

PVin<6.2V, PVin voltage should be accounted for

when calculating control loop parameters.

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