SL40307A-R19KHF datasheet(44/53 Pages) IRF

44 / 53 page

IR3846

44 www.irf.com

August 01, 2013

LAYOUT RECOMMENDATIONS

The layout is very important when designing high

frequency switching converters. Layout will affect

noise pickup and can cause a good design to perform

with less than expected results.

Make the connections for the power components in

the top layer with wide, copper filled areas or

polygons. In general, it is desirable to make proper

use of power planes and polygons for power

distribution and heat dissipation.

The inductor, input capacitors, output capacitors and

the IR3846 should be as close to each other as

possible. This helps to reduce the EMI radiated by the

power traces due to the high switching currents

through them. Place the input capacitor directly at the

PVin pin of IR3846.

The feedback part of the system should be kept away

from the inductor and other noise sources.

The critical bypass components such as capacitors for

PVin, Vin and VCC should be close to their respective

pins. It is important to place the feedback components

including feedback resistors and compensation

components close to Fb and Comp pins.

In a multilayer PCB use at least one layer as a power

ground plane and have a control circuit ground

(analog ground), to which all signals are referenced.

The goal is to localize the high current path to a

separate loop that does not interfere with the more

sensitive analog control function. These two grounds

must be connected together on the PC board layout at

a single point. It is recommended to place all the

compensation parts over the analog ground plane in

top layer.

The Power QFN is a thermally enhanced package.

Based on thermal performance it is recommended to

use at least a 6-layers PCB. To effectively remove

heat from the device the exposed pad should be

connected to the ground plane using vias. Figure

51a-f illustrates the implementation of the layout

guidelines outlined above, on the IRDC3846 6-layer

demo board.

Figure 51a: IRDC3846 Demo board Layout Considerations – Top Layer

- Compensation parts

should be placed

as close as possible

to the Comp pins

- SW node copper is

kept only at the top

layer to minimize the

switching noise

- Single point connection

between AGND &

PGND, should be placed

near the part and kept

away from noise sources

PGND

PVin

Vout

AGND

- Ground path between

VIN- and VOUT- should

be minimized with

maximum copper

- Bypass caps should be

placed as close as

possible to their

connecting pins

- Filled vias placed

under PGND and

PVin pads to help

thermal performance.

PGND

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