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SL40307A-R19KHF 数据表(PDF) 29 Page - International Rectifier |
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SL40307A-R19KHF 数据表(HTML) 29 Page - International Rectifier |
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29 / 53 page ![]() IR3846 29 www.irf.com © 2013 International Rectifier April 29, 2013 | V1.0 TYPICAL OPERATING WAVEFORM DESIGN EXAMPLE The following example is a typical application for IR3846. The application circuit is shown in Figure 37. Vin = PVin = 12V Fs = 600kHz Vo = 1.2V Io = 35A Ripple Voltage = ± 1% * Vo ∆Vo = ± 4% * Vo (for 30% load transient) Enabling the IR3846 As explained earlier, the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage as shown in Figure 31. Figure 31: Using Enable pin for UVLO implementation For a typical Enable threshold of VEN = 1.2 V 2 . 1 2 1 2 (min) EN in V R R R PV (10) EN in EN V PV V R R (min) 1 2 (11) For PVin (min)=9.2V, R1=49.9K and R2=7.5K ohm is a good choice. Programming the frequency For Fs = 600 kHz, select Rt = 39.2 KΩ, using Table 1. Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The FB pin is the inverting input of the error amplifier, which is internally referenced to VREF. The divider ratio is set to equal VREF at the FB pin when the output is at its desired value. When an external resistor divider is connected to the output as shown in Figure 32, the output voltage is defined by using the following equation: 6 5 1 R R V V ref o (12) ref o ref V V V R R 5 6 (13) For the calculated values of R5 and R6, see feedback compensation section. Figure 32: Typical application of the IR3846 for programming the output voltage Bootstrap Capacitor Selection To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin, which is connected to the source of the Control FET. This is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (C1). The operation of the circuit is as follows: When the sync FET is turned on, the capacitor node connected to SW is pulled down to ground. The capacitor charges towards Vcc through the internal bootstrap diode (Figure 33), which has a forward voltage drop VD. The voltage Vc across the bootstrap capacitor C1 is approximately given as: D cc c V V V (14) |
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