SL40307A-R19KHF datasheet(25/53 Pages) IRF

25 / 53 page

IR3846

25 www.irf.com

August 01, 2013

Figure 22: Typical waveforms in tracking mode of

operation: (a) simultaneous, (b) ratiometric

Figure 23: Application Circuit for Simultaneous and

Ratiometric Sequencing

Tracking

and

sequencing

operations

can

implemented to be simultaneous or ratiometric (refer

to Figure 21 and Figure 22). Figure 23 shows typical

circuit configuration for sequencing operation. With

this power-up configuration, the voltage at the Vp pin

of the slave reaches 0.6V before the Fb pin of the

master. If RE/RF =RC/RD, simultaneous startup is

achieved. That is, the output voltage of the slave

follows that of the master until the voltage at the Vp

pin of the slave reaches 0.6 V. After the voltage at the

Vp pin of the slave exceeds 0.6V, the internal 0.6V

reference of the slave dictates its output voltage. In

reality the regulation gradually shifts from Vp to

internal Vref. The circuit shown in Figure 23 can also

be used for simultaneous or ratiometric tracking

operation if Vref of the slave is connected to LGND.

Table 2 summarizes the required conditions to

achieve

simultaneous/ratiometric

tracking

sequencing operations.

Table 2: Required Conditions for Simultaneous /

Ratiometric Tracking and Sequencing (Figure 23)

Operating

Mode

Vref

(Slave)

Required

Condition

Normal

(Non-

sequencing,

Non-tracking)

0.6

(Floating)

Floating

―

Simultaneous

Sequencing

0.6V

Ramp

up from

RA/RB >

RE/RF =

RC/RD

Ratiometric

Sequencing

0.6V

Ramp

up from

RA/RB >

RE/RF >

RC/RD

Simultaneous

Tracking

Ramp

up from

RE/RF =

RC/RD

Ratiometric

Tracking

Ramp

up from

RE/RF >

RC/RD

VREF

This pin reflects the internal reference voltage which is

used by the error amplifier to set the output voltage. In

most operating conditions this pin is only connected to

an external bypass capacitor and it is left floating. A

minimum 100pF ceramic capacitor is required from

stability point of view. In tracking mode this pin should

be pulled to LGND. For margining applications, an

external voltage source is connected to Vref pin and

SL40307A-R19KHF 数据表(PDF) 25 Page - International Rectifier

SL40307A-R19KHF 数据表(HTML) 25 Page - International Rectifier

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

数据表下载

链接网址

SL40307A-R19KHF 数据表(PDF) 25 Page - International Rectifier

SL40307A-R19KHF 数据表(HTML) 25 Page - International Rectifier

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

数据表 下载

链接网址

数据表下载