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SL40307A-R19KHF 数据表(PDF) 34 Page - International Rectifier

部件名 SL40307A-R19KHF
功能描述  Single-Input Voltage, Synchronous Buck Regulator
PDF  53 Pages
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制造商  IRF [International Rectifier]
网页  http://www.irf.com
标志 IRF - International Rectifier

SL40307A-R19KHF 数据表(HTML) 34 Page - International Rectifier

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IR3846
34 www.irf.com
© 2013 International Rectifier
August 01, 2013
to the RSA, β = 1. Please refer to the Remote
Sensing Amplifier section)
Lo
= 0.250 µH
Co = 6 x 100µF, ESR≈3mΩ each
It must be noted here that the value of the
capacitance used in the compensator design must be
the small signal value. For instance, the small signal
capacitance of the 100µF capacitor used in this
design is 56µF at 1.2 V DC bias and 600 kHz
frequency. It is this value that must be used for all
computations related to the compensation. The small
signal value may be obtained from the manufacturer’s
datasheets,
design
tools
or
SPICE
models.
Alternatively, they may also be inferred from
measuring the power stage transfer function of the
converter and measuring the double pole frequency
FLC and using equation (20) to compute the small
signal Co.
These result to:
FLC = 17.4 kHz
FESR = 947 kHz
Fs/2 = 300 kHz
Select crossover frequency F0=100 kHz
Since FLC<F0<Fs/2<FESR, Type III is selected to place
the pole and zeros.
Detailed calculation of compensation Type III:
Desired Phase Margin Θ = 70°
sin
1
sin
1
2
o
Z
F
F
14.1 kHz
sin
1
sin
1
2
o
P
F
F
567.1 kHz
Select:
2
1
5
.
0
Z
Z
F
F
7.05 kHz and
s
P
F
F
5
.
0
3
300 kHz
Select C4 = 2.2nF.
Calculate R3, C3 and C2:
in
osc
o
o
o
V
C
V
C
L
F
R
4
3
2
; R3 = 3.60 kΩ,
Select: R3 = 2.7 kΩ
3
1
3
2
1
R
F
C
Z
; C3 = 8.49 nF,
Select: C3 = 8.2 nF
3
3
2
2
1
R
F
C
P
; C2 = 196 pF,
Select: C2 = 160 pF
Calculate R4, R5 and R6:
2
4
4
2
1
P
F
C
R
; R4 = 127.6 Ω,
Select R4 = 127 Ω
2
4
5
2
1
Z
F
C
R
; R5 = 5.13 kΩ,
Select R5 = 4.02 kΩ

5
6
R
V
V
V
R
ref
o
ref
; R6 = 4.02 kΩ,
Select R6 = 4.02 kΩ
If (β x Vo) equals Vref, R6 is not used.
Setting the Power Good Threshold
In this design IR3846, the PGood outer limits are set
at 95% and 120% of VREF. PGood signal is asserted
1.3ms after Vsns voltage reaches 0.95*0.6V=0.57V
(Figure 37)
. As long as the Vsns voltage is between
the threshold ranges, Enable is high, and no fault
happens, the PGood remains high.
The following formula can be used to set the PGood
threshold. Vout (PGood_TH) can be taken as 95% of Vout.
Choose Rsns1=4.02 KΩ.



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