P8044AH-R0117 datasheet(26/65 Pages) INNOVASIC

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IA8044/IA8344

Data Sheet

SDLC Communications Controller

March 30, 2010

IA211010112-04

http://www.Innovasic.com

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Page 26 of 65

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Table 14. Port 3 Register

INT1

INT0

TxD

RxD

Bit [7]—RD → (P3.7) External Data Memory read strobe, active LOW

Bit [6]—WR → (P3.6) External Data Memory write strobe, active LOW

Bit [5]—T1 → (P3.5) Timer/Counter 1 external input

Bit [4]—T0 → (P3.4) Timer/Counter 0 external input

Bit [3]—INT1 → (P3.3) External Interrupt 1

Bit [2]—INT0 → (P3.2) External Interrupt 0

Bit [1]—TxD → (P3.1) Serial output pin

Bit [0]—RxD → (P3.0) Serial input pin

4.7

Timers/Counters

4.7.1

Timers 0 and 1

The IA8X44 has two 16-bit timer/counter registers, Timer 0 and Timer 1. Both can be configured

for counter or timer operations. In timer mode, the register is incremented every machine cycle,

which means that it counts up after every 12 oscillator periods. In counter mode, the register is

incremented when the falling edge is observed at the corresponding input pin T0 or T1. Because it

takes two machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/24 of the

oscillator frequency. There are no restrictions on the duty cycle, however to ensure proper

recognition of 0 or 1 state, an input should be stable for at least one machine cycle (12 clock

periods).

Four operating modes can be selected for Timer 0 and Timer 1. Two SFRs (TMOD and TCON)

are used to select the appropriate mode.

4.7.2

Mode 0

In Mode 0 the timers operate as an 8-bit timer (TH0/1) with a divide by 32-bit prescalar (TL0/1).

Mode 0 uses all eight bits of TH0/1 and the lower five bits of TL0/1. The upper three bits of

TL0/1 are unknowns. Setting TR0/1 does not reset the registers TH0/1 and TL0/1. As the timer

rolls over from all 1s to all 0s it will set the interrupt flag TF0/1.

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