P8044AH-R0117 datasheet(27/65 Pages) INNOVASIC

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IA8044/IA8344

Data Sheet

SDLC Communications Controller

March 30, 2010

IA211010112-04

http://www.Innovasic.com

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4.7.3

Mode 1

Mode 1 is the same as Mode 0 except that all eight bits of TL0/1 are used instead of just the lower

five bits.

4.7.4

Mode 2

Mode 2 configures TL0/1 as an 8-bit counter with automatic reload from the contents of TH0/1.

Overflow of TL0/1 causes the interrupt TF0/1 to be set and the reload to occur. The contents of

TH0/1 are not affected by the reload.

4.7.5

Mode 3

Mode 3 creates two separate 8-bit counters from TL0 and TH0. TL0 uses the Timer 0 mode bits

from TMOD, TMOD.0 through TMOD.3. TH0 is a timer only (not a counter) and uses Timer 1’s

control bits, TR1 and TF1, for operation. Timer 1 can still be used if an interrupt is not required

by switching it in and out of its own Mode 3. With TMOD.4 and TMOD.5 both high, Timer 1

will stop and hold its count.

4.7.6

Timer Mode (TMOD)

Table 15 presents the values for the Timer Mode register, which contains bits that select the mode

that the timers are to be operated in. The lower nibble controls Timer 0 and the upper nibble

controls Timer 1. Table 16 presents the timer mode select bits.

Table 15. Timer Mode Register

GATE

C/T

GATE

C/T

Bit [7]—GATE → (TMOD.7) If set, enables external gate control for Counter/Timer 1 (pin

INT1 for Counter 1). When INT1 is high, and TR1 bit is set (see TCON register), the

counter is incremented every falling edge on T1 input pin.

Bit [6]—C/T → (TMOD.6) C/T selects Timer 1 or Counter 1 operation. When set to 1, the

counter operation is performed. When cleared to 0, the register will function as a timer.

Bit [5]—M1 → (TMOD.5) Timer 1 mode selector bit.

Bit [4]—M0 → (TMOD.4) Timer 1 mode selector bit.

Bit [3]—GATE → (TMOD.3) If set, enables external gate control for Counter/Timer 0 (pin

INT0 for Counter 0). When INT0 is high, and TR0 bit is set (see TCON register), the

counter is incremented every falling edge on T0 input pin.

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