P8044AH-R0117 datasheet(36/65 Pages) INNOVASIC

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IA8044/IA8344

Data Sheet

SDLC Communications Controller

March 30, 2010

IA211010112-04

http://www.Innovasic.com

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Bit [3]—PT1 → (IP.3) Timer 1 interrupt priority bit

Bit [2]—PX1 → (IP.2) External Interrupt 1 interrupt priority bit

Bit [1]—PT0 → (IP.1) Timer 0 interrupt priority bit

Bit [0]—PX0 → (IP.0) External Interrupt 0 interrupt priority bit

4.9.7

Interrupt Enable Register (IE)

Table 30 presents the interrupt enable register, which contains the global interrupt enable bit and

individual interrupt enable bits. Setting a bit enables the corresponding interrupt.

Table 30. Interrupt Enable Register

–

ET1

EX1

ET0

EX0

Bit [7]—EA → (PCON.7) Enable all interrupts bit

Bit [6]—(PCON.6)

Bit [5]—(PCON.5)

Bit [4]—ES → (PCON.4) SIU interrupt enable bit

Bit [3]—ET1 → (PCON.3) Timer 1 interrupt enable bit

Bit [2]—EX1→ (PCON.2) External Interrupt 1 interrupt enable bit

Bit [1]—ET0→ (PCON.1) Timer 0 interrupt enable bit

Bit [0]—EX0→ (PCON.7) External Interrupt 0 interrupt enable bit

4.10

SIU

—Serial Interface Unit

The SIU is a serial interface customized to support SDLC/HDLC protocol. As such, it supports

Zero Bit insertion/deletion, flags automatic access recognition and a 16-bit CRC. The SIU has

two modes of operation AUTO and FLEXIBLE. The AUTO mode uses a subset of the SDLC

protocol implemented in hardware. This frees the CPU from having to respond to every frame but

limits the frame types. In the FLEXIBLE mode every frame is under CPU control and therefore

more options are available. The SIU is controlled by and communicates to the CPU by using

several SFRs. Data transmitted by or received by the SIU is stored in the 192-byte internal RAM

in blocks referred to as the transmit and receive buffers. The SIU can support operation in one of

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