P8044AH-R0117 datasheet(38/65 Pages) INNOVASIC

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IA8044/IA8344

Data Sheet

SDLC Communications Controller

March 30, 2010

IA211010112-04

http://www.Innovasic.com

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Table 32. Serial Mode Select Clock Mode Bits

SCM

2 1 0

Clock Mode

Data Rate

(bits/sec)a

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Externally clocked

Undefined

Self clocked, timer overflow

Undefined

Self clocked, external 16X

Self clocked, external 32X

Self clocked, internal fixed

–2.4Mb

244

–62.5K

–375K

–187.5K

375K

187.5K

aBased on a12-MHz crystal frequency.

–1 Mbps in loop configuration.

4.10.3 Status/Command Register (STS)

Table 33 presents the Status/Command Register, which provides SIU control from and status to

the CPU. The SIU can read the STS and can write certain bits in the STS. The CPU can read and

write the STS. Accessing the STS by the CPU via two cycle instructions—JBC bit,rel and

MOV bit,C—should not be used. STS is bit addressable.

Table 33. Status/Command Register

TBF

RBE

RTS

BOV

OPB

RBP

Bit [7]—TBF → (STS.7) Transmit buffer full. TBF is set by the CPU to indicate that the

transmit buffer is ready and TBF is cleared by the SIU.

Bit [6]—RBE → (STS.6) Receive buffer empty. RBE is set by the CPU when it is ready

to receive a frame or has just read the buffer. RBE is cleared by the SIU when a frame has

been received. Can be thought of as a Receive Enable.

Bit [5]—RTS → (STS.5) Request to send. This bit is set when the SIU is ready to transmit

or is transmitting. May be written by the SIU in AUTO mode. RTS is only applied to the

external pin in non-loop mode. Can be thought of as a Transmit Enable.

Note: RTS signal at the pin (P1.6) is the inverted version of this bit.

Bit [4]—SI → (STS.4) SIU interrupt. This bit is set by the SIU and should be cleared by

the CPU before returning from the interrupt routine.

Bit [3]—BOV → (STS.3) Receive buffer overrun. The SIU can set or clear BOV.

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