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P8044AH-R0117 数据表(PDF) 28 Page - InnovASIC, Inc |
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P8044AH-R0117 数据表(HTML) 28 Page - InnovASIC, Inc |
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28 / 65 page ![]() IA8044/IA8344 Data Sheet SDLC Communications Controller March 30, 2010 IA211010112-04 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 28 of 65 1-888-824-4184 ® Bit [2]—C/T → (TMOD.2) C/T selects Timer 0 or Counter 0 operation. When set to 1, the counter operation is performed. When cleared to 0, the register will function as a timer. Bit [1]—M1 → (TMOD.1) Timer 0 mode selector bit. Bit [0]—M0 → (TMOD.0) Timer 0 mode selector bit. Table 16. Timer Mode Select Bits M1 M0 Operating Mode 0 0 0 13-bit timer 0 1 1 16-bit timer/counter 1 0 2 8-bit auto-reload timer/counter 1 1 3 Timer 0 –TL0 is a standard 8-bit timer/counter controlled by Timer 0 control bits. TH0 is an 8-bit timer function only, controlled by Timer 1 control bits. 1 1 3 Timer/Counter 1 stopped and holds its count. Can be used to start/stop Timer 1 when Timer 0 is in Mode 3. 4.7.7 Timer Control (TCON) Table 17 presents the timer control register, which provides control bits that start and stop the counters. It also contains bits to select the type of external interrupt desired, edge or level. Additionally, TCON contains status bits showing when a timer overflows and when an interrupt edge has been detected. Table 17. Timer Control Register 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit [7]—TF1 → (TCON.7) Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag should be cleared by software. In Mode 3 this bit is controlled by TH0. Bit [6]—TR1 → (TCON.6) Timer 1 run control bit. If cleared, Timer 1 stops. In Mode 3 this bit controls TH0. Bit [5]—TF0 → (TCON.5) Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag should be cleared by software. Bit [4]—TR0 → (TCON.4) Timer 0 run control bit. If cleared, Timer 0 stops. Bit [3]—IE1→ (TCON.3) Interrupt 1 edge flag. Set by hardware, when falling edge on external pin INT1 is detected cleared when interrupt is processed. |
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